Hi,
In AMBA AHB:-
For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.
q) For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…
What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.
Thanks
I am a Digital Verification Design Engineer.
Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.
I have following questions.
1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?
2) From AHB Master side,…
Why the address boundary for AHB burst should not cross 1KB??
And in case of burst operation, is that every beat the address increment taken care by master?
Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?
what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.
Im new to the ahb protocol can any on give me an idea about retry response, when a retry response is generated from slave side.
I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated.
But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length burst.
Doesn't it mean that INCR is not terminated?
…I noticed that "Multi slave select" is one of the new features in AHB5.
But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?
I think we can do that with AHB3.
What is the major difference between AHB3…
How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…
Hello All,
Here at IP Level verification we have no issues as the Master APB does not latch the PREADY, but at SOC Level with multiple APB Slaves
The Master performs some transaction with APB SLAVE 1 and before switching to APB SLAVE 2 , it disables the…
This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…
I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
Hi,
Can you please help me in writing assertions to take care on multiple transfer in APB bus?
Thanks,
Rakesh
Hi,
I see the Amba Adaptive Traffic Profiles blog and it's interesting.
Is it only a specification ?
Any public domain source code (C++ or Python) or executable to generate the traffic patterns in a commercial simulator ?
Thanks,
David
How to handle below scenario ?
Hi all,
I am new to protocols AHB and AXI.
can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?
Also what these boundaries are for? Does they represent the maximum slave size?
Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…
Hello,
I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.
1) I would like to know how read and write address requests issued…
i am not able to understand working of this CACHE signal pleas explain with simple example.
thank you!
As per spec, the burst length of wrap type should be 2,4,8 or 16. But at the same time it is also mentioned that burst length= AxLEN[7:0] +1, to accommodate the extended burst length of the INCR burst type in AXI4.
If my burst length value is 2 i.e [00000010…
