I am not able to see any visible improvements due to the BURST transfers. The same BURST transfer could be done through multiple SINGLE transfers, in the same number of cycles. Then what is te advantage of having BURST transfers?

I need to add/encorporate AHB interface to a processor with Load/Store Architecture, which has already been designed. But the processor has only data bus for both input and output. Is it possible to still add AHB interface by multiplexing or two separate…

Hi all,

I am new to protocols AHB and AXI.

can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

Also what these boundaries are for? Does they represent the maximum slave size?

Hi sir,

       T1=NON-SEQ

       T2=BUSY

       T3=SEQ

       T4=SEQ

      T5= SEQ

         This is for WRITE operation:

         i am  using a BUSY state for T2. Then my WAIT state for till T3.  I have read from the forum if WAIT state u are using a BUSY transfer, you can change next…

Hi sir,

        I am now new to AHB. In the AHB wrap4 transfer, i can use a second cycle is a busy cycle, and also i am using a WAIT state for first 4 clock .In spec says if u use a busy state then the slave provide a zero wait state. In my case i am using…

HI 

     I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.

    If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer…

The AHB starting address is only a even or odd . If odd  how to calculate the wrap boundary calculation in WRAP4 ,hsize=2.   

Regards

Rajaraman R

Hello All,

            I am using a WRAP4 burst and my HSIZE=O.

           So boundary=(beat * hsize in byte)

                               = 4 *1

                              = 4

          My starting addrss=217

          The wrap4 will increment to 217,218,219,216.

          This is correct or not

why okay response is single cycle?but error,split,retry is two cycle.why?

Hello,

We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

So the questions…

Hi,

Facing the issue:
"MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

Here is the Inputs:

We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
connected…

I am newly learning AHBprotocol  i just want to know what is meaning of single cycle bus master handover?

  1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

  2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

Hi,

Can any one explain me how address decoding is done in amba ahb?

HRESP  is given  for address or data??

hi,

Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

thanks in advance

Hi,

In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

Hi All ,

                      The following figure shows the INCR4 burst transaction.

Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

What are the possible adjustment has to be made for this transaction…

Hi,

 I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

1.I can think of invalid address as the only case. Is there any other scenario?

2. I am performing a INCR4 transfer on AHB side…

Hello All,

  I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.

When  I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?

Scenario : Single…

Hello I want to know the calculation for

HSIZE=2 and Wrap 8

and starting address is 0x4

and how we are doing alignment ???