Dear Community,

I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

a)
I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
When there are Bust…

Hi,

I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections.

Please confirm and where can I find relevant information for this topic.

Thanks,

David

Hi,

 I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

So not sure of the legal ramifications of posting this elsewhere and whether…

According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

        "All signals are sampled on the rising edge of the global clock "

     Q) Should RESET_N also  be sampled on the rising edge only?

Section A3.1.2,  says

   "The AXI protocol…

I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…

What is byte lane in AXI?

In read transfres how the slave indicates the transaction is over?

If the slave is not able to process read request from master, which response is expected from slave?

Why burst must not cross 4kb  in AXI ?

Hii,

Greetings !!

I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

Please someone help me out.

Thanks in advance

Regards

Ujjwal

what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

Why the word boundary in AXI is 4k?

Consider Data interface is 64 bit.
It is Write transfer.
AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

Scenario 1:
Burst -> Address:0, size:3, length:1, burst_type…

Use case which come to my mind is.

1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

2. Where ever there is LIFO (Last In Fist Out) implementations.

Hi All,

                       I am doing single write operation to AXI slave from avalon BFM. The data and address signals

are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

It…

Is interleave and reorder the same concept?

My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

why we need write strobe signal in axi where we generate in our verif env

Thanks

what happen if WVALID asserted before AWVALID ??

How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation

Hi,

I am aware that like other channels, the handshaking signals of the Write Response can assert in any order (that means BVALID and BREADY can assert either together at the same clock edge of one after the other in both the orders). But is there any…

Hi,

I am creating a systemC model for a peripheral which has an AXI4 interface.

Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

Is it available from ARM, a ThirdParty vendor, or the opensource community?

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

Eg. Burst length- Two , Burst size 16 bytes.

Please give me answers for different types of data bus width say for bus width …

What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?