Hi
I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core. Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory…
Hi,
This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
"Synchronous Abort" handler…
Hi ,
I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.
Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…
Hello,
I have been reading and searching for some time and have learned a lot about the MPU on an ARMv7-a. I am attempting to use the Unified Region Base/Size registers to both limit memory access, but also have the "Base" value added to memory references…
Hi,
I am a newbie to the TrustZone architecture. I learned that, in secure world, whether a memory access is secure or not is determined by the NS field in the translation descriptor and, in non-secure world, the NS field will be ignored. I am wondering…
Hello everybody!
I am working on a IMX-6 and i have a little problem with the MMU.
I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information Center and i saw that i have to use this command…
