CPUID information about ARMv8 core

ocean

Hi experts,

I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER？

Thanks.

Answered

Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

Kun.Niu

Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.

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If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world

박주병

First sorry my english writing level. :-)

In non-secure world using android system(linux kernel).

I use big.little core Cortex-A53, Cortex-A57

I was tested to 2case.

previous stage.

1. Linux allocation memory using(malloc or mmap)

…

Answered

Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

Kay

Hi Experts,

I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

When I run world shared memory test on a single core (using affinity), it works…

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brk instrustion

hostia

Hi arm experts,

I wrote some simple C functions to check if the result of memcpy is expected after enable MMU and data cache on Cortex-A53. The assembly (got by disassembling with aarch64-none-elf-objdump) of the one of these functions…

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CA72 transactions IDs

Jay Zhao

In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores.

But in CA72, I can't find such descriptions.

In my simulation, tt seems that…

Answered

RK3399: how to configure Compute Library to use specific cores

fset89

I am testing armnn+compute library on my RK3399. I want to measure the inference time using only the A53 cores. How can I exploit Compute Library functionalities to do so?

Answered

Disable data prefetching in a Cortex-A53 running Android

DNovo

Dear Experts,

I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.

I have tried to include in the Linux kernel code (at kernel/init/main.c) a call…

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AARCH64 banked registers

LdB

I am failing at searches can someone point me to a reference for the banked registers for an FIQ in AARCH64 on a cortexA53

I can find hundreds of references for AARCH32 banked registers but none for AARCH64

I have largely ignored the FIQ to date just…

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VMSAv8-64 and spinlock

Ciro Donnarumma

Hi,

I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

I'm writing bare-metal code, without…

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shareable domain and cache policy problem

zhi

Hi,

I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

Configuring an interrupt source as FIQ at EL1

Sumit Batra

For one of our devices (which uses ARM A53 Core with GICv2) we need to configure one of the interrupt sources as FIQ at EL1.
So is there any support for doing such a thing preferably in any of the branches of linux kernel.

Answered

when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot！

sam0220

when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot！

Intercore interrupts on a53 between EL1 and EL3

atr

We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not getting any interrupts. How to make interrupts work…

About watch point debug excption on Cortex-A53

tao.zeng

Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

In our watch point handler, we first disabled watch point control, then handle debug…

Answered

SMP to suspend an individual core with security OS

astonelin@gmail.com

Hi All,

a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

how to implement a suspend/resume flow on a individual core?

TRM only mentions about how to clean cache and off-line from smp

But how to do a cache flush through…

Which is better of thees CPUs

kasem

Which is better of thees CPUs:

Cortex A53 octa core 1.5 ghz,

Cortex A7 Allwinner T8 Eight core 2.0 ghz,

Cortex A9 Quad-Core 1.8 ghz ?

Answered

shareability attribute for armv8 cortex a-53

MarekBykowski

Hi,

I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

My question is how should I interpret the shareability domain: inner, outer…

Answered

A53 preload mechanism

MarkL

Hi,

I am reading the A53 MP Core doc.

My question is related to instruction preloading in aarch64.

In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

Question 1: Will the PLI instruction first…

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Is there any tool to profile power of a C code on Linux running on Cortex A53?

B Ravikumar

We want to profile the power consumed by an application running over Linux kernel 4.2.x on Cortex A53. Is there any tool which can help here?

regards,
Ravi

Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

thomas_cp

Hi,

I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

There is no L3 cache. So the memory…

[A53] Hex file is Huge when generated fromo ELF

AshishK

Hi ,

If I generate the elf file from the Default bootcode and pagetables , I get a very small size but

after mapping the Stack pointer to SRAM , I am getting a huge HEX file.

Here is the loader file code

============================================…

SMC not going into EL3

yaron alterman

Hello experts,

In my project I need to write some bare metal code in order to boot my software (A VxWorks image), and would like to make the absolute minimum configurations before loading the VxWorks image, which then does the major part of the configurations…

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Cortex-A53 backward compatible with AXI-4 interconnect

Ed Leung

Hi,

The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect…

System level Implementation of Generic Timer in Cortex A53

Vasu

Hi,

Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How is it different from Generic timer…

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