Hello,

I have a question regarding the synchronization of caches on ARMv8 on Multi-Core.

Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes.

The 2 cores did cache a line from RAM:

Hello,

For a CortexA35, when reading the system counter clock frequency CNTFRQ_EL0, I found out that the frequency is 8 MHz.

Is this normal? For a target running in GHz?

The target is i.MX8QXP (Quad-Core CortexA35).

Hello,

I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and…

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2 entries are 2M blocks, and L3 entries are 4K, or…