I have an AXI4 initiator that issues a 32-bit read request to an AXI target (memory) via a 64-bit wide data bus.
I set the ARSIZE parameter to 2.
The data in the target memory are the following:
addr : data
0x000: 64'h 77_66_55_44_33_22_11_00
0x100:…
Warning: the PMIC image for this board must be updated. Please edit io_vxxxf.txt stored in \MB\HB10364A\ and set MBPMIC: to pms_0V85.bin Press any key to continue...
HI All,
I am trying to use FREE RTOS in cortex R5 dual core MCU.
Initially the MCU is in Supervisor mode. But in main function, i want to be a processor mode will be in system mode(0x1F).
But i do not find any instruction how to switch from supervisor…
Hello everyone!
I'm wondering if any Arm Mali GPUs, except for Mali-G78AE, are connected to a SMMU.
I have checked that Mali-G610 isn't connected to SMMU (at least in sysfs & device tree).
It's common to have peripherals isolated via SMMU or…
Following the getting started example here: https://learn.arm.com/learning-paths/microcontrollers/asm/setup/ I cannot get past the Configure the FVP section. The instruction to browse for the FVP provided with the MDK at Keil_v5/ARM/FVP/MPS2_Cortex-M…
ARM IHI 0033C:: Section 3.5.2 Write strobes rules: The first bullet point have 2 sub-points stated below:
The first one states that "Write strobes which correspond to an active byte lane can be HIGH or LOW. A transfer with LOW strobe bits for active…
Hello team,
I have a requirement which says "Periodic software readback of static configuration registers". I'm using ARM R5F. Can you provide me a list of these registers and their addresses and contents?
Thanks and Regards,
Vishwanath Reddy…
I wanted to confirm that the following is the latest version of the ARM trusted board boot requirements (TBBR) - https://developer.arm.com/documentation/den0006/latest/
The document from the above link is noted as being a Beta rather than a final release…
The least significant bit in the LR register specifies that the code at this address is a Thumb instruction and all Cortex-M instructions have Thumb encoding. So this behavior is expected. All instructions of Cortex-M cores must be located on even addresses…
Hello,
As you have found, Event recorder printf is not supported in Arm Development Studio. If you switch to semihosted ("Breakpoint") output, you will see the output in the Arm Development Studio Target Console.
