• Not Answered

    Channel Dependencies for Home Node (HN) in CHI 0

    • AMBA 5 CHI
    102 views
    0 replies
    Started 24 days ago
     by madman
  • Not Answered

    Retry support in CHI 0

    • AMBA 5 CHI
    91 views
    0 replies
    Started 24 days ago
     by madman
  • Not Answered

    PMU event count register PMEVCNTR<n> alway is 0 +1

    • Real Time Operating Systems (RTOS)
    • Cortex-A72
    • 12 (Debug Monitor)
    • performance analysis
    • Armv8-A
    • Debug and Analysis
    1435 views
    2 replies
    Latest 28 days ago
     by Lico.yu
  • Answered

    Interrupt Handling recommendation and spurious IRQ debugging 0

    • GICv3/v4
    • ARMv8 Exception Model
    252 views
    1 reply
    Latest 29 days ago
     by Martin Weidmann
  • Not Answered

    Who actually does the out of ordering of the memory accesses in MPCore? 0

    • Out-of-order Execution
    131 views
    0 replies
    Started 29 days ago
     by Shaibal Ghosh
  • Not Answered

    Cortex-A72 ACP deadlock issue 0

    156 views
    1 reply
    Latest 30 days ago
     by Annie
  • Answered

    What is the purpose of two separate coprocessors (CP10 and CP11) for the armv7-m floating point extension? 0

    • Co-processor Architecture
    • Armv7-M
    • Floating Point
    169 views
    2 replies
    Latest 1 month ago
     by Uma Ramalingam
  • Not Answered

    Cannot Perform MTB Configuration on Dual-Core Cortex-M33 ( i.e., AN521 Image) of MPS2+ Board 0

    • CoreLink SSE-200 Subsystem
    • CoreSight Micro Trace Buffer for the Cortex-M33
    • Cortex-M Prototyping System (V2M-MPS2)
    313 views
    3 replies
    Latest 1 month ago
     by njk
  • Not Answered

    Why the overhead of memcpy() in EL3 is higher than in NS.EL1 (linux kernel module)? 0

    • Juno Arm Development Platform
    • Juno Development Board
    • Armv8-A
    • Cache Architecture
    120 views
    0 replies
    Started 1 month ago
     by icegrave0391
  • Not Answered

    problems of TCM ECC initialized 0

    95 views
    0 replies
    Started 1 month ago
     by problems
  • Not Answered

    Cache and TCM Initialization 0

    97 views
    0 replies
    Started 1 month ago
     by problems
  • Not Answered

    ARMV8 CR52 TCM ECC 0

    81 views
    0 replies
    Started 1 month ago
     by problems
  • Answered

    GICv2 vs GICv3 differences 0

    • GICv2
    • GICv3/v4
    290 views
    1 reply
    Latest 1 month ago
     by Martin Weidmann
  • Not Answered

    Question about the difference in the ACE protocol 0

    • AMBA 4
    • Cache Coherent Interconnect
    137 views
    0 replies
    Started 1 month ago
     by JasonDuh
  • Answered

    ARM®︎ CoreLink™︎ QVN Protocol Specification Document link required 0

    • AMBA
    • CoreLink QVN-400
    195 views
    1 reply
    Latest 1 month ago
     by Ronan Synnott
  • Answered

    A72 ACP deadlock +1

    219 views
    1 reply
    Latest 1 month ago
     by Ronan Synnott
  • Answered

    How much faster is FIQ than IRQ？ 0

    343 views
    2 replies
    Latest 1 month ago
     by qp.harson
  • Not Answered

    Cortex-A53: structure of ALU 0

    107 views
    0 replies
    Started 1 month ago
     by Zvi Vered
  • Not Answered

    Cortex A-53 : R/W data using interleaved mnemonics 0

    97 views
    0 replies
    Started 1 month ago
     by Zvi Vered
  • Answered

    Coretex-A53 : Cache size 0

    231 views
    3 replies
    Latest 1 month ago
     by Ronan Synnott
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