• Not Answered

    how to install anroid in cortex a53 0

    280 views
    0 replies
    Started 8 months ago
    by s nath
  • Not Answered

    Support of immediate Rorate & Shift in STM32 CortexM4 0

    • Cortex-M4
    305 views
    0 replies
    Started 8 months ago
    by N Abid Ali Khan
  • Not Answered

    Include macro in .s file 0

    642 views
    2 replies
    Latest 8 months ago
    by WestfW
  • Not Answered

    Cannot flash or erase the STM32 uC anymore. 0

    777 views
    1 reply
    Latest 8 months ago
    by HenkvW
  • Answered

    Cortex-A32 aarch32, change from HYP mode to SVC mode fail 0

    378 views
    1 reply
    Latest 8 months ago
    by Martin Weidmann
  • Answered

    [Cortex-A] Permission fault due to code region mapped as read/write 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A
    1003 views
    5 replies
    Latest 8 months ago
    by jatron
  • Not Answered

    Cortex A9 L1d cache profiling 0

    • Cortex-A9
    • performance analysis
    • Cache Controllers
    460 views
    1 reply
    Latest 8 months ago
    by Noemietown
  • Not Answered

    Activate ETM in Android Mobile device 0

    • mobile
    • Android
    • CoreSight ETM-A5
    • Debug and Trace
    352 views
    0 replies
    Started 8 months ago
    by Seongyun
  • Not Answered

    arm cortex a9 used in control edge plc 0

    269 views
    0 replies
    Started 8 months ago
    by saneesh
  • Not Answered

    .rodata alignment 0

    • AArch64
    • GNU Assembler
    302 views
    0 replies
    Started 8 months ago
    by BobP
  • Suggested Answer

    In order execution 0

    383 views
    1 reply
    Latest 8 months ago
    by vstehle
  • Suggested Answer

    How to control the Non-Secure MPU exclusively inside the Secure world in the Cortex M33? 0

    • Memory Protection Unit (MPU)
    • TrustZone
    • Cortex-M33
    565 views
    1 reply
    Latest 8 months ago
    by Aurelien_Grange
  • Not Answered

    start second core from psci 0

    • AArch64
    • SMCCC
    • Cortex-A55
    • Armv8-A
    • psci
    • AArch32
    376 views
    0 replies
    Started 8 months ago
    by Nikita bogatov
  • Suggested Answer

    Arm MMU configuration works on (qemu) raspberry(a53) but not on virt(armv7, a53) board 0

    • Cortex-A53
    909 views
    6 replies
    Latest 8 months ago
    by Niklas43
  • Not Answered

    [armv8][cortex-a72] why must flush data cache when I tried to map a SRAM area? 0

    • Armv8-A
    476 views
    1 reply
    Latest 8 months ago
    by Martin Weidmann
  • Answered

    CCA in Armv9 - Making Peripherals Only Accessible from a Realm VM 0

    • virtualization
    • Peripheral Controllers
    • TrustZone
    636 views
    2 replies
    Latest 8 months ago
    by Jay M.
  • Suggested Answer

    SError interrupt due to LDAXRB instruction when disable cache on NXP ls1046a 0

    • Armv8-A
    645 views
    2 replies
    Latest 9 months ago
    by Tony Tu
  • Suggested Answer

    Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations? 0

    • Cortex-R52
    • Cache coherency
    • Cortex-R52+
    871 views
    3 replies
    Latest 9 months ago
    by EllieC
  • Not Answered

    Clear recvBuff 0

    323 views
    0 replies
    Started 9 months ago
    by Rishikeshb1998
  • Not Answered

    Power consumption of CM7 - is there a comparison between manufacturing nodes? 0

    286 views
    0 replies
    Started 9 months ago
    by Tani
<>