• Not Answered

    Basic register write data changes in assembly when NOP added 0

    • Custom SoC
    • Arm Assembly Language (ASM)
    4203 views
    0 replies
    Started 3 months ago
     by nav_kris
  • Not Answered

    Interrupts and pipeline 0

    • Pipeline Control and Execution
    • Interrupt
    4437 views
    0 replies
    Started 3 months ago
     by d.ry
  • Not Answered

    Normal store between exclusive transactions? 0

    • SoC Designer
    • Armv8-A
    • Semaphore
    4741 views
    1 reply
    Latest 3 months ago
     by a.surati
  • Not Answered

    TrustZone vs CMN 0

    4464 views
    0 replies
    Started 4 months ago
     by Hunglin
  • Answered

    [NIC-400 Interconnect] Remap mode 0

    6326 views
    2 replies
    Latest 4 months ago
     by Hieu Ho
  • Suggested Answer

    I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ? 0

    • AXI4
    7042 views
    1 reply
    Latest 4 months ago
     by Christopher Tory
  • Suggested Answer

    Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers. 0

    • AXI4
    6880 views
    1 reply
    Latest 4 months ago
     by Christopher Tory
  • Suggested Answer

    AMBA 5 CHI Memory Attributes 0

    • AMBA 5 CHI
    5781 views
    1 reply
    Latest 4 months ago
     by Christopher Tory
  • Suggested Answer

    Compare the performance of In-order and Out-of-order in AXI protocol 0

    5729 views
    1 reply
    Latest 4 months ago
     by Christopher Tory
  • Suggested Answer

    CHI protocol cache line states 0

    • AMBA 5 CHI
    • SoC Verification
    5807 views
    1 reply
    Latest 4 months ago
     by Christopher Tory
  • Answered

    Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior 0

    • AMBA
    • ACE
    • ACE 5
    • interconnect
    • AMBA 5
    15697 views
    7 replies
    Latest 4 months ago
     by Christopher Tory
  • Not Answered

    How do I use M1 designstart fpga on Nexys4 DDR? 0

    4088 views
    0 replies
    Started 4 months ago
     by Roy Kravitz
  • Not Answered

    Question related to Phases in APB 0

    4351 views
    1 reply
    Latest 4 months ago
     by Colin Campbell
  • Not Answered

    Is M3 DesignStart similar to M7 Design Kit? (I don't yet have M7 Design Kit) 0

    • Cortex-M7
    • Cortex-M3
    • DesignStart
    4708 views
    1 reply
    Latest 4 months ago
     by Andy Neil
  • Not Answered

    Design considerations for implementing flash program download 0

    • CoreSight Architecture
    • SWD
    • Debug Access Port (DAP)
    4917 views
    0 replies
    Started 5 months ago
     by DonVerilog
  • Not Answered

    How to process raw data from monitor and convert it into set of commands + data exchange? 0

    4661 views
    0 replies
    Started 5 months ago
     by aditya raja
  • Not Answered

    ARM-A15 SoC integration for Simulation (VCS) How to Enable traces for debug 0

    4845 views
    0 replies
    Started 5 months ago
     by Moti88
  • Answered

    I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0

    6940 views
    1 reply
    Latest 5 months ago
     by aditya raja
  • Not Answered

    Coresight Architecture: Is it possible to include AHB ROM tables as part of system ROM table? 0

    • CoreSight Architecture
    • CoreSight
    5557 views
    0 replies
    Started 6 months ago
     by Vignesh J
  • Not Answered

    Executable name in DS-5 Linux project 0

    • DS-5 Development Studio
    • executable
    • compilation
    • Linux
    5293 views
    0 replies
    Started 6 months ago
     by Yakov Erlich
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