• Answered

    Why does Cortex-R kernel only support Thumb-2? 0

    • Cortex-R
    • Cortex-A
    • Thumb2
    4225 views
    4 replies
    Latest over 5 years ago
    by Kun.Niu
  • Answered

    In Cortex-R4, the interrupt from which part to send to the core? 0

    • Cortex-R
    • Cortex-A
    • Cortex-R4
    3346 views
    3 replies
    Latest over 5 years ago
    by Yasuhiko Koumoto
  • Answered

    Cortex-R doesn't have MMU, is this has some advantages? +1

    • Processor
    • Cortex-A
    2530 views
    2 replies
    Latest over 5 years ago
    by Jens Bauer
  • Answered

    What's the difference between ETM and Debug? 0

    • Cortex-R
    • Cortex-R4
    5854 views
    2 replies
    Latest over 5 years ago
    by Kun.Niu
  • Answered

    What are hints? 0

    • Armv7-A
    • Armv7-R
    3234 views
    3 replies
    Latest over 5 years ago
    by Juha Aaltonen
  • Answered

    What will be happened if I insert a store instruction behind a LDREX instruction for accessing the same address? 0

    • Armv8-A
    • Armv8-R
    1853 views
    1 reply
    Latest over 5 years ago
    by Martin Weidmann
  • Answered

    Usage of Split/Lock Configuration +1

    • Cortex-R
    • Cortex-R5
    • Cortex-A
    3670 views
    4 replies
    Latest over 5 years ago
    by Martin Weidmann
  • Answered

    Application note on R4 and R5 differences +1

    • Cortex-R
    • Cortex-R5
    • Cortex-R4
    4902 views
    5 replies
    Latest over 5 years ago
    by Jerome Decamps - 杜尚杰
  • Not Answered

    ARM Cortex-R5 based Lock-step feature demonstration real time application? 0

    • Cortex-R
    • Cortex-R5
    5857 views
    5 replies
    Latest over 5 years ago
    by Ravinder
  • Answered

    What does "low interrupt latency" means 0

    • Cortex-R
    • AXI
    • Cortex-R4
    9040 views
    11 replies
    Latest over 5 years ago
    by David Harriman-Smith
  • Answered

    How to test " Lock-Step " is working on Cortex-R5 ? 0

    • Cortex-R
    • Cortex-R5
    2800 views
    1 reply
    Latest over 5 years ago
    by Jon Taylor
  • Answered

    Lock-Step mode execution on Cortex-R5 0

    • Cortex-R
    • Cortex-R5
    17833 views
    5 replies
    Latest over 6 years ago
    by Ravinder
  • Answered

    Cortex-R prefetch behavior? Does it cross page boundary? +1

    3054 views
    2 replies
    Latest over 6 years ago
    by Yasuhiko Koumoto
  • Answered

    How to calculate the CPI for ARM Cortex-R4 0

    • Cortex-R
    6261 views
    3 replies
    Latest over 6 years ago
    by Peter Harris
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