• Answered

    TrustZone in CortexR +1

    • Cortex-R
    • virtualization
    • TrustZone
    3949 views
    3 replies
    Latest over 1 year ago
    by 42Bastian Schick
  • Answered

    Debug Unit Cortex - R 0

    3544 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann
  • Answered

    Is CPSR.F settable through debug port? (e.g. JTAG) +1

    • Cortex-R5
    • CPSR
    • Debugging
    3240 views
    3 replies
    Latest over 1 year ago
    by 42Bastian Schick
  • Answered

    Instruction Fault Generation +1

    2749 views
    2 replies
    Latest over 1 year ago
    by techguyz
  • Answered

    Inner/Outer Cacheability in Cortex V8-R +1

    3632 views
    3 replies
    Latest over 1 year ago
    by David Harriman-Smith
  • Answered

    Memory barrier when accessing strongly ordered memory +1

    3251 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann
  • Answered

    ARM assembly instruction for writing Zero to SPSR +1

    2349 views
    1 reply
    Latest over 1 year ago
    by 42Bastian Schick
  • Not Answered

    Inner/Outer share ability in Cortex R52 0

    920 views
    0 replies
    Started over 1 year ago
    by Reco
  • Not Answered

    TCM arbitration hazard: Considerations for Firmware 0

    • Cortex-R
    • Cortex-R5
    905 views
    0 replies
    Started over 1 year ago
    by c0deface
  • Answered

    Cortex R5 behavior when a masked imprecise/asynchronous abort occurs +1

    5900 views
    6 replies
    Latest over 1 year ago
    by Martin Weidmann
  • Answered

    Data Abort on read, although write can be executed without any abort. +1

    • Armv7 Exception Model
    • Memory
    3554 views
    3 replies
    Latest over 1 year ago
    by r4c00n
  • Not Answered

    The Peripherals memory map of FVP_BaseR_Cortex-R52x1 0

    • Cortex-R52
    • Fixed Virtual Platforms (FVPs)
    • PrimeCell UART (PL011)
    1013 views
    0 replies
    Started over 1 year ago
    by Jex1x
  • Not Answered

    Is it OK to bypass all clock gates in Cortex-R52? 0

    • Cortex-R52
    • Clocking Structures & Timing Mechanisms
    • SoC FPGA
    1147 views
    0 replies
    Started over 1 year ago
    by Zack Yang
  • Not Answered

    reference source code to verify the Cortex-R52 0

    • Cortex-R52
    • Evaluation Boards
    2071 views
    1 reply
    Latest over 1 year ago
    by Jorney
  • Answered

    ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence 0

    • Cortex-A53
    • Cortex-R
    • CoreLink CCI-400 Cache Coherent Interconnect
    • Cache coherency
    • Cortex-R5
    • Cortex-A
    4894 views
    6 replies
    Latest over 1 year ago
    by Sandeep Bobba
  • Not Answered

    PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1 0

    • Cortex-R52
    • Cortex-R
    • api
    965 views
    0 replies
    Started over 2 years ago
    by Reco
  • Not Answered

    Cache ECC in Cortex-R5 & Event bus +1

    • Cortex-R
    • Cortex-R5
    • Cache
    2811 views
    2 replies
    Latest over 2 years ago
    by Johnson Berry
  • Not Answered

    When is Cortex-R5 Virtual Peripheral AXI bus used? 0

    • Cortex-R
    • AXI
    • Cortex-R5
    1206 views
    0 replies
    Started over 2 years ago
    by Etienne Alepins
  • Not Answered

    Hypervisor Mode to System Mode in R52 cortex 0

    • Cortex-R
    • Cortex-R5
    1390 views
    0 replies
    Started over 2 years ago
    by Himanshu Khanna
  • Not Answered

    Porting FreeRTOS On R-52 Cortex +1

    • Cortex-R52
    • Cortex-R
    • Real Time Operating System (RTOS)
    2837 views
    1 reply
    Latest over 2 years ago
    by Georgia James
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