• Not Answered

    TCM arbitration hazard: Considerations for Firmware 0

    • Cortex-R
    • Cortex-R5
    820 views
    0 replies
    Started over 1 year ago
    by c0deface
  • Answered

    Cortex R5 behavior when a masked imprecise/asynchronous abort occurs +1

    5462 views
    6 replies
    Latest over 1 year ago
    by Martin Weidmann
  • Answered

    Data Abort on read, although write can be executed without any abort. +1

    • Armv7 Exception Model
    • Memory
    3188 views
    3 replies
    Latest over 1 year ago
    by r4c00n
  • Not Answered

    The Peripherals memory map of FVP_BaseR_Cortex-R52x1 0

    • Cortex-R52
    • Fixed Virtual Platforms (FVPs)
    • PrimeCell UART (PL011)
    950 views
    0 replies
    Started over 1 year ago
    by Jex1x
  • Not Answered

    Is it OK to bypass all clock gates in Cortex-R52? 0

    • Cortex-R52
    • Clocking Structures & Timing Mechanisms
    • SoC FPGA
    986 views
    0 replies
    Started over 1 year ago
    by Zack Yang
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