• Not Answered

    Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1? 0

    • AArch64
    • Armv8-A
    • AArch32
    314 views
    1 reply
    Latest 7 hours ago
    by 42Bastian Schick
  • Not Answered

    How to handle Interrupt with certain interrupt ID in Arm Trusted Firmware 0

    • Arm Trusted Firmware
    36 views
    0 replies
    Started 9 hours ago
    by whexy
  • Not Answered

    CortexA53, FreeRTOS and interrupts 0

    642 views
    2 replies
    Latest 12 hours ago
    by Mark 35r4
  • Not Answered

    Jetson TX2 cortex-a57 crash after enabling mmu 0

    • Memory Management Unit (MMU)
    305 views
    0 replies
    Started 22 hours ago
    by josecm
  • Not Answered

    Rowhammer bug on ARM 0

    • Cortex-A72
    • Armv8-A
    277 views
    0 replies
    Started 1 day ago
    by Frederick
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