• Answered

    AHB revisions from AHB3 to AHB5 0

    • AMBA
    • AHB
    12008 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell
  • Answered

    Burst termination with BUSY transfer on AHB 0

    • AMBA
    • AHB
    11704 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell
  • Answered

    Regarding retry response +1

    • AMBA
    • AHB
    10903 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell
  • Answered

    APB3 Slave responding when PSEL = 0 +1

    • APB
    • AMBA
    11921 views
    2 replies
    Latest over 1 year ago
    by vshankar11
  • Answered

    What is expected from response if in WRAP txn in AHB is un-aligned. +1

    • AHB-Lite
    • AHB
    10552 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell
  • Answered

    AMBA +1

    • APB
    • AMBA
    • Bus Architecture
    10395 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell
  • Answered

    Does AHB-Lite Protocol require the master processor to be pipelined? +1

    • AHB-Lite
    • Processor Architecture
    11342 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell
  • Answered

    APB process when pstrb = "0000" or "0101" during write transaction 0

    10967 views
    2 replies
    Latest over 1 year ago
    by Hyunkyu
  • Not Answered

    Dealing with Inout Ports - design and testbench writing 0

    • Verilog
    9586 views
    0 replies
    Started over 1 year ago
    by Kedhar Guhan
  • Answered

    How do I add AHB interface to a processor with Load Store Architecture? 0

    • Processor Architecture
    • AMBA 2 AHB Interface
    • AHB
    10983 views
    2 replies
    Latest over 1 year ago
    by Kedhar Guhan
  • Not Answered

    Axi4 Write Transaction 0

    • AMBA
    • AXI4
    10652 views
    1 reply
    Latest over 1 year ago
    by vstehle
  • Not Answered

    State Machine for AHB-Lite Protocol 0

    • AHB-Lite
    • AHB
    11368 views
    3 replies
    Latest over 1 year ago
    by Colin Campbell
  • Not Answered

    Amba Adaptive Traffic Profiles question 0

    • AMBA
    9810 views
    1 reply
    Latest over 1 year ago
    by Matteo Maria Andreozzi
  • Answered

    [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? +1

    • AXI
    11141 views
    2 replies
    Latest over 1 year ago
    by Zax
  • Not Answered

    Assertion for Multiple Transfer on APB Bus 0

    • APB
    • AMBA
    • Bus Architecture
    10802 views
    2 replies
    Latest over 1 year ago
    by Rakesh Venkatesan
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