• Answered

    cortex a53 : How to detect cached data is invalid ? (use ddr memory) 0

    • Cache Controllers
    • Cache Management
    5608 views
    4 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Bare metal startup code for Cortex-78 CPUs 0

    3021 views
    6 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Answered

    Taking exceptions from EL1 to EL1: Problems with SVC 0

    • Cortex-A53
    • AArch64
    • ARMv8 Exception Model
    5904 views
    12 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Difference between SP_EL1 and SPSEL + MOV 0

    3587 views
    6 replies
    Latest over 2 years ago
     by 42Bastian Schick
  • Not Answered

    physical and virtual timer. 0

    2692 views
    2 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Answered

    Arm cortex a53 giving abort when mmu is enabled and reading data from device region 0

    • Cortex-A53
    • Memory Management Unit (MMU)
    4616 views
    8 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Problem switching from EL3 to non-secure EL1 0

    • Cortex-A35
    • AArch64
    • ARMv8 Exception Model
    3697 views
    5 replies
    Latest over 2 years ago
     by zhak
  • Not Answered

    如何获取arm64位的fast model license 0

    7768 views
    1 reply
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Translation error at level1 in armv8 A72 cortex 0

    5092 views
    11 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Cortex X1 - New Branch to create 0

    2627 views
    3 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    arm64 kvm虚拟机中数据一致性问题 0

    6448 views
    1 reply
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Why there is no translation tables concatenation for stage 1 of VA translation? 0

    3838 views
    3 replies
    Latest over 2 years ago
     by Cliff B
  • Suggested Answer

    Share aarch64 page tables created by Linux with SMMU 0

    • Cortex-A53
    • CoreLink MMU-500 System Memory Management Unit
    • Corelink
    • CoreLink CCI-400 Cache Coherent Interconnect
    • CoreLink CCI-400
    • Cortex-A5
    • ACE
    • CHI
    • Cortex-A
    • Linux
    20250 views
    5 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    Download the old versions of ARM A64 Instruction Set Architecture 0

    • Base ISAs
    • Documentation
    • Arm64
    2074 views
    1 reply
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Not Answered

    No segmentation fault when expected with aligned load and store 0

    • SIMD and Vector Processing Instructions
    • Armv8-A
    • NEON
    • Software Development
    7457 views
    5 replies
    Latest over 2 years ago
     by Sheila
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