• Answered

    I am looking for ECC insertion method (any instruction) on any address with ARM Cortex M4. +1

    3158 views
    5 replies
    Latest over 4 years ago
    by Anuj
  • Answered

    In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not? +1

    • AMBA
    • AHB
    3163 views
    1 reply
    Latest over 4 years ago
    by Yasuhiko Koumoto
  • Answered

    Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)? +1

    • Cortex-M7
    • Cache
    • Cortex-M
    2666 views
    4 replies
    Latest over 4 years ago
    by Yasuhiko Koumoto
  • Answered

    AXI3 & AXI4 wrap burst length 0

    • AXI3
    • AXI4
    9204 views
    5 replies
    Latest over 4 years ago
    by Utkarsh Jain
  • Not Answered

    CMSIS DSP Correlation 0

    4227 views
    4 replies
    Latest over 4 years ago
    by Aidan Walton
  • Answered

    Embedded assembly function problem 0

    • Cortex-A9
    • NEON
    • Cortex-A
    3133 views
    3 replies
    Latest over 4 years ago
    by Yasuhiko Koumoto
  • Answered

    Need to invalidate L1 cache after DMA on Cortex A9 +1

    • Cortex-A9
    • Cache
    • Cortex-A
    5692 views
    3 replies
    Latest over 4 years ago
    by Rohan
  • Not Answered

    My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag? 0

    • Cortex-M
    • Cortex-M4
    4762 views
    8 replies
    Latest over 4 years ago
    by Yasuhiko Koumoto
  • Answered

    What is differene between cortex A, Cortex M and Cortex R series of ARM? 0

    • Cortex-R
    • Cortex-A
    • Cortex-M
    16554 views
    3 replies
    Latest over 4 years ago
    by tanveermalik
  • Answered

    Help configuring A57 performance counters 0

    • Cortex-A57
    • Arm Development Studio
    • ds-5
    • performance
    • Cortex-A
    2841 views
    2 replies
    Latest over 4 years ago
    by Michael
  • Answered

    How to configure Cortex-A57 PMU 0

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    • 64-bit
    6138 views
    5 replies
    Latest over 4 years ago
    by Michael
  • Answered

    Issue in writing a data in PMU register +1

    • Cortex-A
    • Cortex-A7
    6801 views
    9 replies
    Latest over 4 years ago
    by Yasuhiko Koumoto
  • Answered

    Is there an intrinsic to store 3 float values? +1

    • GNU Compilers Collection (GCC)
    5889 views
    9 replies
    Latest over 4 years ago
    by Peter Harris
  • Answered

    In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response? 0

    • AMBA
    • System Architecture
    • Bus Architecture
    • AHB
    8159 views
    9 replies
    Latest over 4 years ago
    by Colin Campbell
  • Answered

    IAR Embedded Workbench ARM compiler 0

    3487 views
    1 reply
    Latest over 4 years ago
    by Yasuhiko Koumoto
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