• Answered

    A simple arm program question, could help me? 0

    4922 views
    5 replies
    Latest over 7 years ago
     by G. Goodwin L. Pitos
  • Answered

    float behaivior on AARCH64 +1

    • Armv7-A
    • AArch64
    • NEON
    8363 views
    6 replies
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Answered

    DSP instruction for x*x + y*y. Does it exist? 0

    • Cortex-M
    • Cortex-M4
    12116 views
    14 replies
    Latest over 7 years ago
     by Matic
  • Answered

    about tail chaning of Cortex-M0 0

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    5862 views
    4 replies
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Answered

    I am looking for ECC insertion method (any instruction) on any address with ARM Cortex M4. +1

    4463 views
    5 replies
    Latest over 7 years ago
     by Anuj
  • Answered

    In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not? +1

    • AMBA
    • AHB
    5644 views
    1 reply
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Answered

    Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)? +1

    • Cortex-M7
    • Cache
    • Cortex-M
    3910 views
    4 replies
    Latest over 7 years ago
     by amanda_s
  • Answered

    AXI3 & AXI4 wrap burst length 0

    • AXI3
    • AXI4
    13884 views
    5 replies
    Latest over 7 years ago
     by Utkarsh Jain
  • Not Answered

    CMSIS DSP Correlation 0

    6519 views
    4 replies
    Latest over 7 years ago
     by Aidan Walton
  • Answered

    Embedded assembly function problem 0

    • Cortex-A9
    • NEON
    • Cortex-A
    4791 views
    3 replies
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Not Answered

    What does PMCEID0_EL0 determine for the the PMU? Performance monitor config 0

    • Cortex-A57
    • Cortex-A
    4318 views
    3 replies
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Answered

    Need to invalidate L1 cache after DMA on Cortex A9 +1

    • Cortex-A9
    • Cache
    • Cortex-A
    7815 views
    3 replies
    Latest over 7 years ago
     by Rohan
  • Not Answered

    My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag? 0

    • Cortex-M
    • Cortex-M4
    7790 views
    8 replies
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Answered

    What is differene between cortex A, Cortex M and Cortex R series of ARM? 0

    • Cortex-R
    • Cortex-A
    • Cortex-M
    32283 views
    3 replies
    Latest over 7 years ago
     by tanveermalik
  • Answered

    Help configuring A57 performance counters 0

    • Cortex-A57
    • Arm Development Studio
    • ds-5
    • performance
    • Cortex-A
    4767 views
    2 replies
    Latest over 7 years ago
     by Michael
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