• Suggested Answer

    Floating-point computing capabilities of Cortex-A9 and Cortex-A53 0

    • Armv7-A
    • Armv8-A
    975 views
    2 replies
    Latest over 1 year ago
    by vstehle
  • Answered

    IO coherency 0

    810 views
    1 reply
    Latest over 1 year ago
    by vstehle
  • Not Answered

    How can I build ATF opteed in aarch32 EL3 runtime software(BL32)? 0

    • Arm Trusted Firmware
    • Armv7-A
    • Armv8-A
    • TrustZone
    1444 views
    2 replies
    Latest over 1 year ago
    by Emmy0
  • Answered

    Cycle counter: on which ARM will the code successfully run? 0

    • Cortex-A53
    • Armv7-A
    • Raspberry Pi 3
    • Architectures
    1506 views
    6 replies
    Latest over 1 year ago
    by 42Bastian Schick
  • Not Answered

    Error: unknown mnemonic `mcr' for aarch64? 0

    • AArch64
    • AArch32
    2726 views
    2 replies
    Latest over 1 year ago
    by vstehle
  • Suggested Answer

    turning off instruction and data prefetch on A53 0

    1394 views
    4 replies
    Latest over 1 year ago
    by DougM
  • Suggested Answer

    Linux kernel boot-up issue in ARM Cortex-A78 while accessing virtual memory 0

    • Kernel Developers
    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A78
    2155 views
    5 replies
    Latest over 1 year ago
    by selgan01
  • Answered

    NEON Intrinsics Performance +1

    • AArch64
    • Armv8-A
    5415 views
    6 replies
    Latest over 1 year ago
    by RW-sec
  • Not Answered

    PCIe real connection to devices 0

    • pcie
    2742 views
    3 replies
    Latest over 1 year ago
    by vstehle
  • Suggested Answer

    Neon Instrinsics complex number algorithms 0

    • NEON
    2029 views
    2 replies
    Latest over 1 year ago
    by sriram_s
  • Not Answered

    Cortex-A53 switching from EL2 to EL1 0

    • Cortex-A53
    • Baremetal
    9715 views
    22 replies
    Latest over 1 year ago
    by bluehat
  • Answered

    AXI4 - Data before address - why? 0

    • Address
    • AXI4
    3586 views
    6 replies
    Latest over 1 year ago
    by af_23
  • Answered

    Disable Cache L1 et L2 Armv8 0

    • Cortex-A72
    • Cache
    • Armv8-A
    12018 views
    8 replies
    Latest over 1 year ago
    by Kael Hong
  • Answered

    Custom bootable image 0

    3145 views
    2 replies
    Latest over 1 year ago
    by segfault
  • Not Answered

    Why performance is higher on LITTLE cores? 0

    • big.LITTLE
    • performance
    • multithreading
    6918 views
    14 replies
    Latest over 2 years ago
    by zois
<>