• Answered

    Reset Management Register Functioanlity in ARM v8 +1

    • Cortex-A57
    • AArch64
    • Cortex-A
    • AArch32
    4956 views
    2 replies
    Latest over 7 years ago
     by Peter Rielly
  • Answered

    Trap control and instruction enable/disable in ARMv8 +1

    • EL2
    • NEON
    4228 views
    1 reply
    Latest over 7 years ago
     by Peter Rielly
  • Answered

    System Error Interrupts in ARM V8 +1

    • EL1
    • Cache
    6900 views
    1 reply
    Latest over 7 years ago
     by Peter Rielly
  • Answered

    Usage of YIELD instruction in ARM V8 +1

    • C
    5918 views
    1 reply
    Latest over 7 years ago
     by Peter Rielly
  • Answered

    shareable attribute in armv8 0

    • Cortex-A53
    • Armv7-A
    • AArch64
    • Armv8-A
    • Cortex-A
    7006 views
    2 replies
    Latest over 7 years ago
     by Harish G
  • Answered

    shareability memory attribute 0

    • Cortex-A57
    • Cortex-A
    • Cortex-A8
    6130 views
    2 replies
    Latest over 7 years ago
     by hostia
  • Answered

    SMMU initialization +1

    • Cortex-A
    • Cortex-A7
    7239 views
    2 replies
    Latest over 8 years ago
     by Dav
  • Answered

    How SMMU will override the memory attribute of the master which have MMU/MPU embedded? 0

    • Cortex-A53
    • Cortex-A
    5804 views
    3 replies
    Latest over 8 years ago
     by Martin Weidmann
  • Answered

    How to use those crypto extension to write asm code? +1

    • Armv8-A
    7215 views
    5 replies
    Latest over 8 years ago
     by Martin Weidmann
  • Answered

    D-side prefetch Cortex-A8 0

    • Cortex-A9
    • Cortex-A
    • Cortex-A8
    5307 views
    2 replies
    Latest over 8 years ago
     by Andreas Hauser
  • Answered

    ARM Trusted Firmware, number of cpu cores.. 0

    • Arm Trusted Firmware
    • Armv8-A
    5928 views
    1 reply
    Latest over 8 years ago
     by Peter Rielly
  • Answered

    how to understand ARMv8 exception level1 secure/non-secure MMU? +1

    • EL1
    • EL3
    • AArch64
    • Armv8-A
    7436 views
    1 reply
    Latest over 8 years ago
     by Peter Rielly
  • Answered

    Exception / Interrupt for Cortex-A15 0

    • Cortex-A15
    • Cortex-A
    • Interrupt
    4270 views
    2 replies
    Latest over 8 years ago
     by Michihiro Yamamoto
  • Answered

    The Non-Secure Access IDentity (NSAID) of TZC-400 0

    • AXI
    • CoreLink TZC-400
    7523 views
    2 replies
    Latest over 8 years ago
     by wangyong
  • Answered

    What will I get if I try to access SCR in cp15 when my core is in non secure mode. +1

    • TrustZone
    5322 views
    4 replies
    Latest over 8 years ago
     by Jay Zhao
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