• Answered

    R5 DSM tarmac format <time> <scale> option 0

    3144 views
    1 reply
    Latest over 5 years ago
    by Peter Rielly
  • Suggested Answer

    GIC order of completion of interrupts 0

    • Generic Interrupt Controller
    5339 views
    4 replies
    Latest over 5 years ago
    by josecm
  • Suggested Answer

    What's the relationship between exclusive access and memory cacheable in Cortex A53? 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    5636 views
    3 replies
    Latest over 5 years ago
    by Emmy0
  • Answered

    Armv8 Memory Mapping 0

    • Cortex-A53
    • Cortex-A57
    • Armv8-A
    • Cortex-A
    8063 views
    7 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Which component will program TZASC? 0

    • Armv7-A
    • TrustZone
    8169 views
    5 replies
    Latest over 5 years ago
    by raghu.ncstate
  • Suggested Answer

    how "Early Write Acknowledgement" is encoded on AXI AxCache ? equal to "bufferable"? 0

    • Armv7-A
    • AXI
    • Armv8-A
    6301 views
    2 replies
    Latest over 5 years ago
    by astonelin@gmail.com
  • Answered

    Transition to secure monitor flow on ARMv8 +1

    • ARMv8 Exception Model
    • Security
    • Armv8
    • Armv8-A
    5562 views
    1 reply
    Latest over 5 years ago
    by Peter Rielly
  • Suggested Answer

    How to ensure the safety of SP_EL0 0

    • ARMv8 Exception Model
    • Armv8-A
    5208 views
    2 replies
    Latest over 6 years ago
    by chendader
  • Answered

    Flat memory model 0

    6277 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Virtual IRQ/FIQ exceptions with ARMv8 and no GIC 0

    5136 views
    4 replies
    Latest over 6 years ago
    by Peter Rielly
  • Suggested Answer

    Control access to L2 cache 0

    5431 views
    5 replies
    Latest over 6 years ago
    by christoph8446
  • Suggested Answer

    What is meaning of Logical MMU ? 0

    • TrustZone
    4482 views
    2 replies
    Latest over 6 years ago
    by Peter Rielly
  • Answered

    Which component set the NS bit in SCR ? 0

    • Architecture
    • CHI
    • TrustZone
    • Armv8-M
    10623 views
    2 replies
    Latest over 6 years ago
    by Sahil
  • Answered

    Memory map for ARMv8-M TrustZone SOC's 0

    • Address
    • TrustZone
    • Armv8-M
    • Memory
    22938 views
    6 replies
    Latest over 6 years ago
    by raghu.ncstate
  • Answered

    How to do the ARM state change between 64-bit and 32-bit Guest OS on Hypervsor? 0

    5386 views
    1 reply
    Latest over 6 years ago
    by Peter Rielly
<>