• Answered

    How to run AArch32 code in DS-5 AArch64? +1

    • Arm Development Studio
    • AArch64
    • AArch32
    8320 views
    6 replies
    Latest over 6 years ago
     by ldivya47
  • Answered

    Cortex M0+ what means "optionally shifted" at some instructions like EOR (register) +1

    3461 views
    2 replies
    Latest over 6 years ago
     by Volker Kugler
  • Answered

    How to know if the processor is in EL0 state on armv8? +2

    • ARMv8 Exception Model
    • Armv8
    11121 views
    6 replies
    Latest over 6 years ago
     by Ajeesh
  • Answered

    Vector Table for ARMv8 (cortex A57) 0

    • Cortex-A53
    • EL1
    • Cortex-A57
    • EL3
    • EL2
    • ARMv8 Exception Model
    • EL0
    • Cortex-A
    9518 views
    2 replies
    Latest over 6 years ago
     by Ajeesh
  • Answered

    Porting code From Cortex-A9 to Cortex-R7 0

    • Armv7
    • Cortex-A9
    • Arm Assembly Language (ASM)
    • Cortex-R7
    4893 views
    3 replies
    Latest over 6 years ago
     by Ajeesh
  • Answered

    Can I map the code/data memory as device memory +1

    3949 views
    3 replies
    Latest over 6 years ago
     by Peter Rielly
  • Answered

    Porting code from Cortex-A9 to Cortex-A57 0

    • Cortex-A57
    • Cortex-A9
    • AArch64
    • Arm Assembly Language (ASM)
    • AArch32
    5036 views
    3 replies
    Latest over 6 years ago
     by Peter Rielly
  • Answered

    How to add particular interface (I2C or SPI) to the trustzone from software in qualcomm MSM8909 platform. +1

    • ACE
    • TrustZone
    • Armv8-M
    • Interface
    9250 views
    1 reply
    Latest over 6 years ago
     by Peter Rielly
  • Answered

    Pending interrupt status +1

    • Processor Architecture
    • Interrupt
    7495 views
    2 replies
    Latest over 6 years ago
     by Peter Rielly
  • Answered

    TrustZone environment for ARMv8-M? +2

    • Armv8-A
    • TrustZone
    • Armv8-M
    8815 views
    2 replies
    Latest over 6 years ago
     by loquat3
  • Answered

    Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8? 0

    • ARMv8 Exception Model
    • Armv8
    5875 views
    2 replies
    Latest over 6 years ago
     by Mughees
  • Answered

    ARMv8-M FPCCR_S.TS from secure to secure +1

    4646 views
    4 replies
    Latest over 6 years ago
     by Peter Rielly
  • Answered

    MMU initialization is same for cortex A9 & A8 ? +1

    4084 views
    1 reply
    Latest over 6 years ago
     by Peter Rielly
  • Answered

    How to use Cortex-a53 FVP for AArch32 platform in DS-5? 0

    • Arm Development Studio
    • AArch64
    • Fixed Virtual Platforms
    • Cortex-A53 FVP
    • Cortex-A
    • AArch32
    6535 views
    4 replies
    Latest over 6 years ago
     by ldivya47
  • Answered

    Asynchronous External Abort and Trustzone +1

    6999 views
    6 replies
    Latest over 6 years ago
     by Vincent Siles
<>