• Not Answered

    unaligned data fetch in Cortexa9 0

    • Cortex-A9
    • Cortex-A
    3520 views
    1 reply
    Latest over 7 years ago
     by Matt Sealey
  • Answered

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    • ds-5
    • eclipse
    7620 views
    8 replies
    Latest over 7 years ago
     by Sean
  • Answered

    Reason Behind EL2 in non-secured state ARMv8 +1

    • EL1
    • EL2
    5170 views
    1 reply
    Latest over 7 years ago
     by Matt Sealey
  • Answered

    Integrated Debug Functionality in ARM v8 +1

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    2918 views
    1 reply
    Latest over 7 years ago
     by Matt Sealey
  • Not Answered

    Fixed Virtual Platform Usage 0

    • ds-5
    • model
    • Fixed Virtual Platforms (FVPs)
    4253 views
    2 replies
    Latest over 7 years ago
     by techguyz
  • Not Answered

    DS-5 support for development boards 0

    2564 views
    1 reply
    Latest over 7 years ago
     by Matt Sealey
  • Answered

    Cache maintanance operation to PoC +1

    • Cortex-A9
    • Cache
    • Cortex-A
    • Cortex-A8
    9544 views
    4 replies
    Latest over 7 years ago
     by Luke
  • Not Answered

    Can one ARM core debug another one in an MP/bigLITTE system? 0

    • big.LITTLE
    5299 views
    3 replies
    Latest over 7 years ago
     by Matt Sealey
  • Answered

    Toolchain difference gcc-eabihf and gcc-eabi 0

    8537 views
    1 reply
    Latest over 7 years ago
     by Matt Sealey
  • Answered

    Does load/store-exclusive violate Hypervisor Transparency? 0

    • Armv7-A
    • Armv8-A
    4312 views
    1 reply
    Latest over 7 years ago
     by Matt Sealey
  • Not Answered

    Issue FIQ pending arm trusted firmware 0

    • Juno Arm Development Platform
    • Arm Trusted Firmware
    4715 views
    5 replies
    Latest over 8 years ago
     by armdev
  • Answered

    Funny asymmetry with banked register names 0

    • Armv7-A
    • Cortex-A
    • Cortex-A7
    6233 views
    5 replies
    Latest over 8 years ago
     by Juha Aaltonen
  • Answered

    Does CCI-400 guarantees cache coherency between secure and non-secure worlds? 0

    • Cortex-A53
    • Cortex-A57
    • big.LITTLE
    • CoreLink CCI-400
    • Cache
    • Cortex-A
    4581 views
    3 replies
    Latest over 8 years ago
     by Kay
  • Answered

    How to set inner of outer shareability on page table entry WITHOUT TEX remap?? 0

    • Cortex-A
    • TrustZone
    5639 views
    3 replies
    Latest over 8 years ago
     by Matt Sealey
  • Not Answered

    Compatibility between gcc-arm and ds-5 compiler 0

    • Toolchain
    • gcc_toolchain_ds-5
    • GCC
    • arm-gcc
    • DS-5 Ultimate Edition
    • compatibility
    6184 views
    1 reply
    Latest over 8 years ago
     by Matt Sealey
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