• Suggested Answer

    Where is 'The level associated with MMU faults' referenced multiple times in Exception Register documentation 0

    • AArch64
    • Documentation
    • Memory Management Unit (MMU)
    1183 views
    2 replies
    Latest over 1 year ago
     by Martin Weidmann
  • Answered

    How to generate delay in CPU? +1

    • Cortex-A72
    • Arm Assembly Language (ASM)
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    8 replies
    Latest over 1 year ago
     by David06
  • Answered

    why the inter-core SGI interrupt cannot be trigged on GICv3 hardware 0

    • Generic Interrupt Controller (GIC)
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    10 replies
    Latest over 1 year ago
     by ivan_m@rocketmail.com
  • Answered

    Use of WVALID signal in AXI +1

    • AXI
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    3 replies
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    Differences between Armv7 to Armv8? 0

    154962 views
    16 replies
    Latest over 1 year ago
     by CyLim
  • Answered

    Virtual interrupt EOI mode & irq state 0

    • GICv2
    • GICv3/v4
    • virtualization
    4427 views
    3 replies
    Latest over 2 years ago
     by HenryW1991
  • Answered

    Application note on R4 and R5 differences +1

    • Cortex-R
    • Cortex-R5
    • Cortex-R4
    9460 views
    7 replies
    Latest over 2 years ago
     by EllieC
  • Suggested Answer

    VMSAv8-64 -- worst-case effects of misprogramming of the Contiguous bit +2

    • Armv7-A
    • AArch64
    13114 views
    5 replies
    Latest over 2 years ago
     by wrw
  • Suggested Answer

    Share aarch64 page tables created by Linux with SMMU 0

    • Cortex-A53
    • CoreLink MMU-500 System Memory Management Unit
    • Corelink
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    • CoreLink CCI-400
    • Cortex-A5
    • ACE
    • CHI
    • Cortex-A
    • Linux
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    5 replies
    Latest over 2 years ago
     by Zenon Xiu (修志龙）
  • Answered

    Why is there an ACP interface for many ARM processors? 0

    • AXI
    32270 views
    8 replies
    Latest over 2 years ago
     by marekx
  • Answered

    Running armv7 binaries on armv8 0

    • Armv7-A
    • Armv8-A
    40171 views
    8 replies
    Latest over 2 years ago
     by Cyan101
  • Answered

    ARM/THUMB instructions that change execution path? 0

    • Thumb
    109895 views
    77 replies
    Latest over 2 years ago
     by jakebunt
  • Answered

    How to do the ARM state change between 64-bit and 32-bit? 0

    • 32-bit
    • AArch64
    • Armv8-A
    • 64-bit
    • AArch32
    87934 views
    10 replies
    Latest over 3 years ago
     by Su40mmer
  • Answered

    range of BL instruction in arm state 0

    • Armv7-A
    • Armv7-R
    35878 views
    10 replies
    Latest over 3 years ago
     by chevestong
  • Answered

    In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY? +1

    • EL1
    • Armv7-A
    • EL0
    • Memory Management Unit (MMU)
    • Hypervisor
    26356 views
    3 replies
    Latest over 3 years ago
     by Martin Weidmann
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