• Answered

    In aarch32 state, what is the mechanism to switch to aarch64 in software? 0

    • EL1
    • AArch64
    • AArch32
    9793 views
    5 replies
    Latest over 7 years ago
     by cray
  • Answered

    Issue in writing a data in PMU register +1

    • Cortex-A
    • Cortex-A7
    10670 views
    9 replies
    Latest over 7 years ago
     by Yasuhiko Koumoto
  • Answered

    Cache type and cache operation sequence +1

    • AMBA
    • ACE
    • Cache
    6351 views
    3 replies
    Latest over 7 years ago
     by Michael Williams
  • Not Answered

    ARM Context ID Register & Process Context Switch 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    • Cortex-A8
    15557 views
    10 replies
    Latest over 7 years ago
     by onion
  • Answered

    Reordering between multiple loads 0

    • Cache
    • Cortex-A
    • Cortex-A8
    6905 views
    7 replies
    Latest over 7 years ago
     by Hemant
  • Answered

    Pseudocode for saturation (Oh no, not again) 0

    • Cortex-A
    • Cortex-A7
    3658 views
    2 replies
    Latest over 8 years ago
     by Juha Aaltonen
  • Answered

    Register 'names' in instruction descriptions +1

    • Cortex-A
    • Cortex-A7
    9139 views
    3 replies
    Latest over 8 years ago
     by Juha Aaltonen
  • Answered

    Why I can't find the performance monitoring event for all Instructions count? How to get instructions event for my ARMV7 Cortex-A9 by PMU? 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    7843 views
    6 replies
    Latest over 8 years ago
     by hello_arm
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