• Answered

    ARM CCN (Cache Coherent Network) question 0

    • CoreLink CCN-512 Cache Coherent Network
    12967 views
    2 replies
    Latest over 3 years ago
     by MarekBykowski
  • Answered

    What are the necessary preconditions to load a guest into EL1 from EL2? +1

    • EL1
    • EL2
    • ARMv8 Exception Model
    • Armv8-A
    • Hypervisor
    25649 views
    2 replies
    Latest over 3 years ago
     by MarekBykowski
  • Answered

    determine a page size on armv8 +1

    • Armv8-A
    • Memory Management Unit (MMU)
    22841 views
    2 replies
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    [DS-5] Is it possible to set a watchpoint on a spec reg? +1

    • DS-5 Debugger
    18728 views
    1 reply
    Latest over 3 years ago
     by Martin Weidmann
  • Answered

    ARMCC: How to generate assembly 0

    • GNU GCC
    14793 views
    9 replies
    Latest over 4 years ago
     by hannahxx
  • Answered

    Looking for an eval board with octa core Armv8 CPU 0

    • AArch64
    16791 views
    11 replies
    Latest over 4 years ago
     by 42Bastian Schick
  • Answered

    Can we reset L2 subsystem for cortex-A57? +1

    • Cortex-A57
    • Cortex-A
    7212 views
    1 reply
    Latest over 4 years ago
     by MarekBykowski
  • Answered

    Invalid entry - mmu page tables +1

    • System MMU
    6615 views
    1 reply
    Latest over 4 years ago
     by MarekBykowski
  • Answered

    ARMv7-A: Cache maintenance operation by VA, performance +1

    • Cache coherency
    • Cache
    • Cortex-A
    • Cortex-A8
    10891 views
    8 replies
    Latest over 4 years ago
     by MarekBykowski
  • Answered

    indirect branches in ARMv8 0

    • Cortex-A53
    • AArch64
    • Armv8-A
    • Cortex-A
    7073 views
    2 replies
    Latest over 4 years ago
     by Martin Weidmann
  • Answered

    Multi core L1 cache coherent +1

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    5985 views
    3 replies
    Latest over 4 years ago
     by Jorney
  • Answered

    ARM cortext A53 Physical Address Flush +1

    • Cortex-A53
    • AArch64
    • Cortex-A
    • AArch32
    9239 views
    7 replies
    Latest over 5 years ago
     by MarekBykowski
  • Answered

    SMC not going into EL3 +1

    • Cortex-A53
    • Cortex-A
    14176 views
    16 replies
    Latest over 5 years ago
     by yaron alterman
  • Answered

    [Cortex-A53] STP instruction stores out of the specified memory +1

    • Cortex-A53
    • Cortex-A
    • Armv8.1-A
    6374 views
    4 replies
    Latest over 5 years ago
     by Emmy0
  • Answered

    Cortex A53 : Cache policy setting 0

    • Cortex-A53
    • Cache
    • Cortex-A
    7330 views
    4 replies
    Latest over 5 years ago
     by MarekBykowski
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