• Answered

    Xilinx FPGA Block ROM is used as FLASH and how to load the program in to this? 0

    • Cortex-M0
    • FPGA
    • JTAG
    • Keil
    • DesignStart
    • ULink2
    • Cortex-M
    • SWD
    • Block
    • Memory
    6874 views
    4 replies
    Latest over 3 years ago
     by Joseph Yiu
  • Answered

    how to handle lockup state in M33 +1

    11279 views
    14 replies
    Latest over 3 years ago
     by d.ry
  • Answered

    Debugging a Cortex-M0 Hard Fault 0

    • Armv6
    • Cortex-M0
    • Armv6-M
    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Debugging
    81447 views
    6 replies
    Latest over 3 years ago
     by delinaty
  • Answered

    Cortex-M7: Force Precise Exception on Bus Fault +1

    26913 views
    4 replies
    Latest over 3 years ago
     by Daniel Oliveira
  • Not Answered

    Cortex-M3 frequency 0

    4717 views
    2 replies
    Latest over 3 years ago
     by Joseph Yiu
  • Answered

    Fail to connect with CM0DSEvel 0

    • Cortex-M0
    • DesignStart
    5163 views
    5 replies
    Latest over 3 years ago
     by RickyChen
  • Answered

    Rookie needs help +1

    2462 views
    1 reply
    Latest over 3 years ago
     by Joseph Yiu
  • Answered

    COrtex M7 cache hit rate measurement +1

    • Cortex-M7
    • performance
    • Cache Management
    3463 views
    1 reply
    Latest over 3 years ago
     by Joseph Yiu
  • Not Answered

    How to detect FPU in Cortex M? 0

    • Cortex-M
    3610 views
    1 reply
    Latest over 3 years ago
     by Joseph Yiu
  • Not Answered

    Does "LDRD" instruction cause "UNDEFINSTR" error on Cortex-M4? 0

    • Cortex-M4
    9795 views
    9 replies
    Latest over 3 years ago
     by Gavin Li
  • Answered

    What USB Blaster cable? +1

    • FPGA
    • USB
    • DesignStart
    • Cortex-M
    • Cortex-M Prototyping System (V2M-MPS2)
    10638 views
    7 replies
    Latest over 3 years ago
     by Javier4
  • Answered

    Nuvoton M2351 Keil RTX5 Hard faults on OS initialization 0

    • Cortex-M23
    • TrustZone for Armv8-M
    • Armv8-M
    3757 views
    2 replies
    Latest over 3 years ago
     by Joseph Yiu
  • Not Answered

    Problem with Keil setup for NXP MKV 0

    2300 views
    1 reply
    Latest over 3 years ago
     by Joseph Yiu
  • Answered

    How to verify the Cortex-M0 thumb instructions ? I found one chip( RAM &FLASH is OK) when it run LDR relative instructions,the program is in Hardfault。But others run the same code is OK 0

    13353 views
    19 replies
    Latest over 3 years ago
     by hyue
  • Not Answered

    Please assist with Usage Fault /Illegal unaligned load or store Cortex M7 Keil MDK-PRO 0

    • Cortex-M7
    • 3 (HardFault)
    • 6 (UsageFault)
    • Debug and Analysis
    5755 views
    4 replies
    Latest over 3 years ago
     by Joseph Yiu
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