• Answered

    Explanation of cycles on pre and post index-addressing in case of Load and Store instructions. +1

    • Cortex-M
    • Cortex-M4
    2582 views
    2 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Answered

    Is offset of 30 in load and store instructions shows an exceptional case? +1

    • Cortex-M
    • Cortex-M4
    1659 views
    1 reply
    Latest over 3 years ago
    by Joseph Yiu
  • Answered

    Interface Cortex M4 and PSRAM with different power supply voltage +1

    • Cortex-M
    • Cortex-M4
    1858 views
    1 reply
    Latest over 3 years ago
    by Joseph Yiu
  • Answered

    How does matrix4x2 implement in busmatrix? +1

    • Cortex-M3
    • Cortex-M
    2014 views
    1 reply
    Latest over 3 years ago
    by Joseph Yiu
  • Answered

    How to use compiled Hex file from Keil on windows to the design_start? +1

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    1956 views
    1 reply
    Latest over 3 years ago
    by Joseph Yiu
  • Answered

    Cortex-M4 Suspend/Resume Interrupts 0

    • Cortex-M
    • Cortex-M4
    2584 views
    1 reply
    Latest over 3 years ago
    by Joseph Yiu
  • Answered

    How cortex-M4 handles data hazard situations in the pipeline? 0

    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    • AHB
    2888 views
    2 replies
    Latest over 3 years ago
    by HimanshuDoshi19
  • Answered

    How to understand the behavior of hazard in Cortex-M4? 0

    • Cortex-M
    • Cortex-M4
    2844 views
    2 replies
    Latest over 3 years ago
    by HimanshuDoshi19
  • Answered

    Example of instructions, doesn't use functional unit at all? 0

    • Cortex-M
    • Cortex-M4
    5297 views
    8 replies
    Latest over 3 years ago
    by HimanshuDoshi19
  • Answered

    Difference in the current consumption for different register place for few instructions +1

    • Cortex-M
    • Cortex-M4
    2667 views
    4 replies
    Latest over 3 years ago
    by HimanshuDoshi19
  • Answered

    How to get to know the exact instruction address or find the instruction address for least current consumption? +1

    • Cortex-M
    • Cortex-M4
    4517 views
    4 replies
    Latest over 3 years ago
    by Joseph Yiu
  • Answered

    Variation in the current consumption due to memory address and offset value? 0

    • AHB-Lite
    • Cortex-M
    • Cortex-M4
    3366 views
    4 replies
    Latest over 3 years ago
    by HimanshuDoshi19
  • Answered

    Current Variation due to Functional Unit activation or deactivation 0

    • Cortex-M
    • C
    • Cortex-M4
    4405 views
    6 replies
    Latest over 3 years ago
    by HimanshuDoshi19
  • Answered

    When will be the Release of "The Definitive Guide to Cortex M7" ?? 0

    • Cortex-M7
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    4223 views
    3 replies
    Latest over 3 years ago
    by Cat
  • Answered

    Present program counter address +1

    • Armv7-M
    4371 views
    1 reply
    Latest over 3 years ago
    by Joseph Yiu
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