• Not Answered

    How to simulate the NIC? 0

    696 views
    2 replies
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    Are RLAST/WLAST signals required low when no transaction is pending/VALID is low? 0

    • AMBA
    • AXI4
    619 views
    1 reply
    Latest over 1 year ago
     by Colin Campbell
  • Suggested Answer

    AXI4 Narrow and possibly unaligned READ 0

    1902 views
    4 replies
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    Can HTRANS change from IDLE to NONSEQ during AHB error response? 0

    • AHB-Lite
    • AHB5
    820 views
    1 reply
    Latest over 1 year ago
     by Colin Campbell
  • Suggested Answer

    How are packets routed from a master to the correct slave in a multi-slave AXI system? 0

    • AXI4
    707 views
    1 reply
    Latest over 1 year ago
     by Colin Campbell
  • Not Answered

    How to connect Master AHB lite to AHB5 Slave 0

    763 views
    1 reply
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    AHB - Lite protocal 0

    1214 views
    4 replies
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    Difference btw AXI3 and AXI4 0

    • AMBA
    • AXI3
    • AXI4
    • Interface
    36789 views
    7 replies
    Latest over 1 year ago
     by Chris06
  • Suggested Answer

    How should AXI slave handle with illegal write strobe. 0

    1019 views
    1 reply
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    Cortex-m0 interrupt_demo simulation issue +1

    • Cortex-M0
    • Simulation
    • GPIO
    • Microcontroller
    • DesignStart
    • Cortex-M
    • System Design
    • Interrupt
    8102 views
    10 replies
    Latest over 1 year ago
     by Adnan Ashraf
  • Answered

    Control signals during burst termination with BUSY transfer on AHB 0

    • AHB
    1543 views
    1 reply
    Latest over 1 year ago
     by Colin Campbell
  • Answered

    uDMA Transfer 0

    • PrimeCell µDMAController (PL230)
    1992 views
    2 replies
    Latest over 1 year ago
     by PrasanthV
  • Answered

    HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0

    4985 views
    2 replies
    Latest over 1 year ago
     by Tapas
  • Answered

    One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0

    4653 views
    2 replies
    Latest over 1 year ago
     by Tapas
  • Answered

    AXI4 - Data before address - why? 0

    • Address
    • AXI4
    3619 views
    6 replies
    Latest over 1 year ago
     by af_23
<>