• Answered

    AXI4 - read data interleaving 0

    • AMBA
    • AXI
    • AXI4
    • Interface
    25317 views
    9 replies
    Latest over 1 year ago
    by hayk
  • Suggested Answer

    hi. amba 3.0 axi interleaving 0

    • AMBA
    • AMBA 3
    • AXI
    8254 views
    9 replies
    Latest over 3 years ago
    by George ZHAO
  • Answered

    如何理解PoC,CCN-5xx中的L3如何maintenance? 0

    • Maintenance
    • chinese
    • poc,l3
    • 中文
    7719 views
    8 replies
    Latest over 5 years ago
    by steven
  • Answered

    Support for pipelining flops in AXI +1

    • AXI
    • AXI4
    7892 views
    5 replies
    Latest over 5 years ago
    by Xingguang Feng
  • Answered

    How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size? +1

    • AMBA
    • AXI
    • ACE-Lite
    • Cortex-A
    • Cortex-A7
    2550 views
    1 reply
    Latest over 5 years ago
    by Xingguang Feng
  • Answered

    如何理解Cortex-A57只包含GIC CPU Interface? 0

    • Processor
    • chinese
    • Cortex-A57
    • Cortex-A
    • 中文
    • 处理器
    5335 views
    10 replies
    Latest over 5 years ago
    by wangyong
  • Answered

    如何理解read-allocate / write-allocate in AXI4 spec 0

    • Processor
    • chinese
    • AXI4
    • Cache
    • 中文
    • 处理器
    4674 views
    1 reply
    Latest over 6 years ago
    by Xingguang Feng
  • Answered

    question about burst cross 4KB boundary 0

    • Processor
    • chinese
    • AXI
    • 中文
    • 处理器
    2344 views
    3 replies
    Latest over 6 years ago
    by Xingguang Feng
  • Answered

    TrustZone service API 0

    • Tool
    • chinese
    • api
    • service
    • 工具
    • 中文
    • TrustZone
    6272 views
    13 replies
    Latest over 6 years ago
    by Xingguang Feng
  • Answered

    Asynchrous External Data Abort in ARMv7 +1

    • Processor
    • chinese
    • Cortex-A
    • 中文
    • Cortex-A7
    • 处理器
    10421 views
    12 replies
    Latest over 6 years ago
    by Xingguang Feng
  • Answered

    AXI FIXED burst ; Wr/Rd narrow transactions. +1

    • AMBA
    • AXI
    6175 views
    1 reply
    Latest over 6 years ago
    by Xingguang Feng
  • Answered

    CA7 MPCore中如何判断Core处于Non-Secure state? 0

    • Processor
    • chinese
    • mp_core
    • 中文
    • Cortex-A7
    • 处理器
    2951 views
    3 replies
    Latest over 6 years ago
    by Liwenhao
  • Answered

    AXI WR address channel info arriving before, or, after WR data channel info. 0

    • AXI
    7527 views
    4 replies
    Latest over 6 years ago
    by Xingguang Feng
  • Answered

    请问如何理解Secure和Non-secure? 0

    • Processor
    • chinese
    • Armv7
    • vector_table
    • 中文
    • secure
    • 处理器
    8951 views
    10 replies
    Latest over 6 years ago
    by Song Bin 宋斌
  • Answered

    CoreSight / ETM / CTI等等,它们之间的关系? +1

    • Processor
    • chinese
    • Cortex-A57
    • Armv7
    • corsight
    • Armv8
    • 中文
    • 处理器
    5018 views
    1 reply
    Latest over 6 years ago
    by Xingguang Feng
>