• Answered

    The code of app is freertos , the chip has a bootloader, The chip run on Cortex M0 +2

    3037 views
    2 replies
    Latest over 3 years ago
     by hyue
  • Answered

    Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results corrupted stack data abort. Debugger not factor. +1

    27403 views
    5 replies
    Latest over 3 years ago
     by timholt
  • Answered

    Audio mixing efficiently and hard realtime requirment +1

    • algorithms
    • audio
    • Digital Signal Processor (DSP)
    • Cortex-M4
    • STM32 F4
    3982 views
    1 reply
    Latest over 3 years ago
     by Trampas
  • Answered

    How to remap the vector table location? The core of chip is cortex M0 +1

    2247 views
    1 reply
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    What are the necessary preconditions to load a guest into EL1 from EL2? +1

    • EL1
    • EL2
    • ARMv8 Exception Model
    • Armv8-A
    • Hypervisor
    25664 views
    2 replies
    Latest over 3 years ago
     by MarekBykowski
  • Answered

    custom board based on cortex M0 toggle pins not responding. +1

    • Cortex-M0
    2724 views
    2 replies
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72 +1

    • Cortex-A72
    • AArch64
    23352 views
    1 reply
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    Bootloader. VTOR, BOOTPROT FUSE, JUMP to app and other related questions +1

    • Cortex-M0
    • Cortex-M
    15947 views
    5 replies
    Latest over 3 years ago
     by Andy Neil
  • Answered

    Cortex A9 core locks and cant't stop it +1

    • Debug Tools and Test Methods
    25633 views
    1 reply
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    Optimised GPU convolution for low memory integrated devices -such as arm processors /GPUs? +2

    • Mali GPU (Midgard Architecture)
    • Machine Learning (ML)
    • Mali OpenCL SDK
    35610 views
    2 replies
    Latest over 3 years ago
     by abhi.verma
  • Answered

    Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"? +1

    • AArch64
    • Armv8-A
    • System MMU
    27354 views
    2 replies
    Latest over 3 years ago
     by Branden Sherrell
  • Answered

    NVIC_EnableIRQ : enables only one interrupt at a time? +1

    18488 views
    22 replies
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    SRAM reading problem using FMC at STM32H743. +1

    • Cortex-M7
    3769 views
    1 reply
    Latest over 3 years ago
     by Andy Neil
  • Answered

    Is return stack buffer implemented in Zync 7000 Soc +1

    • Cortex-A9
    • Branch Prediction
    22597 views
    1 reply
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    Is there a maximum length of compile path ? +1

    • GNU
    10491 views
    4 replies
    Latest over 3 years ago
     by ksp
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