• Discussion

    IDE Recommendation

    • Cortex-M3
    • IDEs and Tool Suites
    • Cortex-M
    9014 views
    6 replies
    Latest 2 months ago
    by Andy Neil
  • Answered

    AHB-lite Slave Burst Operation 0

    • AHB-Lite
    5602 views
    4 replies
    Latest 3 months ago
    by eugch
  • Suggested Answer

    I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) 0

    11207 views
    6 replies
    Latest 3 months ago
    by Bill Westfeild
  • Answered

    AXI transaction 0

    4810 views
    3 replies
    Latest 3 months ago
    by Colin Campbell
  • Not Answered

    If FIQ is routed to EL3 can it read/write the GICv2 registers from EL3 even if Secure Extension are implemented by both ARM and GIC? 0

    3382 views
    0 replies
    Started 3 months ago
    by kvrajiv
  • Answered

    how to calculate unaligned address for APB? +1

    16029 views
    8 replies
    Latest 3 months ago
    by Colin Campbell
  • Suggested Answer

    APB4 PSTRB 0

    3925 views
    1 reply
    Latest 3 months ago
    by Colin Campbell
  • Not Answered

    AHB Lite 0

    4880 views
    1 reply
    Latest 3 months ago
    by Colin Campbell
  • Not Answered

    Porting to U-boot driver model and device tree control (for ARM-based design) 0

    • Peripheral Devices
    • U-Boot
    6134 views
    1 reply
    Latest 4 months ago
    by rwl
  • Not Answered

    Ulink pro debugging in custom SoC 0

    • Custom SoC
    • ulinkpro
    • SoC Verification
    3461 views
    0 replies
    Started 4 months ago
    by ronit
  • Suggested Answer

    JTAG/SWD and entering debug monitor 0

    • Debug Adapters
    9131 views
    2 replies
    Latest 4 months ago
    by vaiyawa
  • Not Answered

    Design considerations for implementing flash program download 0

    • CoreSight Architecture
    • SWD
    • Debug Access Port (DAP)
    10388 views
    3 replies
    Latest 4 months ago
    by Mohamed Nasser
  • Not Answered

    Using sram instead of a flash memory in ASIC implementation 0

    • SoC Implementation
    • SRAM
    • SoC FPGA
    • Debugging
    4130 views
    0 replies
    Started 4 months ago
    by Mohamed Nasser
  • Not Answered

    Behaviour of CHI Receiver during race condition from RUN to DEACTIVATE 0

    • AMBA
    • AMBA 5 CHI
    • CHI
    • Bus Architecture
    • AMBA 5
    4181 views
    0 replies
    Started 4 months ago
    by amit
  • Not Answered

    In APB, Why do we use enable signal? (Don't care about PREADY) 0

    4518 views
    0 replies
    Started 5 months ago
    by INNS
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