If there are multiple SPIs pending, our GIC-400 acts seemingly abnormally.

Reading out GICC_IAR to acknowledge the pending interrupt leads to an invalid ID value which looks like OR-ed values from the simultaneously pending SPIs.

In my understanding, GICC_IAR…

While there are multiple interrupts pending, reading GICC_IAR results in an invalid SPI number which is OR-ed value from simultaneously pending ones.

For example, if SPI3 (ID = 19) and SPI16 (ID = 48) become pending at the same time (not exactly, but…

How can we route the GICv2 interrupt to the particular core ? ( I have A55 Quard core CPU )

Do we have any example or sample code or any sequence for setting the GIC register ?