• SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval

    Bernhard Lang
    Bernhard Lang

    I am evaluating the SWD-Port of the Cortex-M0 Designstart using the obfuscated component of the Eval distribution AT510-MN-80001-r2p0-00rel in a Modelsim Simulation.

    For that purpose I composed a minimal system with ROM, RAM and ROMTABLE. It runs a test…

    • 6 months ago
    • DesignStart
    • DesignStart forum
  • Cortex-M3 softcore minimal SoC

    TinyLabs
    TinyLabs

    Hello all,

    After getting frustrated with the Xilinx design start guide I created a minimal SoC implementation of CM3 using fusesoc. It currently runs on Arty but could be made to run on other FPGAs that have a fusesoc supported backend.

    Both the Xilinx…

    • 8 months ago
    • DesignStart
    • DesignStart forum
  • why does the loop in Keil run one more time?

    ChangeTheWorld
    ChangeTheWorld

    Hi 

    I use designStart cortex-m3 with ram and rom which inplemented by the internal ram in FPGA board.

    And then I successfully connect it with Keil through JTAG.

    And I try to run the simple function below:

    uint8_t i = 0;
    uint8_t k = 50;
    
    for(i = 0;i…

    • 10 months ago
    • DesignStart
    • DesignStart forum
  • Cycle model build issue - ../../../../cortexm3_rtl

    MikeBoston
    MikeBoston

    make compile SIMULATOR=ius DSM=yes

    xmvlog: *W,NOTIND: unable to access -INCDIR ../../../../cortexm3_rtl/logical/cm3_tpiu/verilog (No such file or directory).

    Fails because cortexm3_rtl/ is not present in the downloaded ARM designStart files.

    Any suggestions…

    • over 1 year ago
    • DesignStart
    • DesignStart forum
  • Pre-silicon Software Development with Arm Models for Cortex-A5 DesignStart

    Rob Kaye
    Rob Kaye

    Arm DesignStart is enhancing the Cortex-A5 package to help custom chip designers to expand market opportunities and develop richer experiences. The new package helps to reduce the development time of Arm-based Linux-capable chips. Designers can now take advantage…

    • over 1 year ago
    • DesignStart
    • DesignStart blog
  • does ARM Cortex-M0 DesignStart support SWD debugger?

    sieg70
    sieg70

    I am studying the ARM Cortex-M0 DesignStart. I found there are debug port SWDIOTMS and SWCLKTCK in the port list of cmsdk_mcu.v, and there are CPU options which defines the CPU's feature.

    I configured the parameter DBG = 1 in the cmsdk_mcu.v Line37…

    • Answered
    • 10402.zip
    • over 4 years ago
    • DesignStart
    • DesignStart forum
  • Case study: RelChip turns up the heat with Arm DesignStart

    Chris Shore
    Chris Shore

    Aiming to push the boundaries of high-temperature electronics, RelChip has established itself in a niche market with the first microcontroller for extreme environmental products — those that operate from a chilly -55°C to a scorching 225°C.…

    • over 1 year ago
    • DesignStart
    • DesignStart blog
  • Case study: accelerated chip design for drones and cameras with Arm DesignStart

    Chris Shore
    Chris Shore

    At some point in almost every action movie or TV show, an evil villain hacks into a camera, surveillance system or drone to wreak mayhem on unwitting victims. That’s exactly the kind of activity that NeoWine, a security integrated circuit (IC) company…

    • over 1 year ago
    • DesignStart
    • DesignStart blog
  • Info: DesignStart compilation tool

    mprakash2
    mprakash2

    For the kind attention of users who have downloaded any of the following DesignStart packages.

    • DesignStart Eval Cortex-M0 and Cortex-M3
    • DesignStart Pro Cortex-M0 and Cortex-M3
    • DesignStart FPGA Cortex-M1 and cortex-M3

    The above packages should be compiled…

    • over 1 year ago
    • DesignStart
    • DesignStart forum
  • Case study: Evolving intelligent devices for immersive experiences

    Chris Shore
    Chris Shore

    Inuitive develops intelligent vision technologies for deployment in applications such as augmented and virtual reality, drones, robotics and autonomous vehicles. Founded in 2012 by Israeli high-tech veterans Shlomo Gadot and Dor Zepeniuk, the Israel-based…

    • over 1 year ago
    • DesignStart
    • DesignStart blog
  • Cortex-M0 DesignStart clock specifications

    estebanFuerte
    estebanFuerte

    Hello together!

    Are there any specifications/limitation for the clock input to the Cortex-M0 DesignStart Processor regarding:

    • Frequency?
    • Duty Cycle?
    • Stability?

    Thank you and best regards,

    Stefan

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • Cortex-M0 DesignStart Prototyping kit makefiles

    elisorin
    elisorin

    Unlike the Design kit makefiles, in which tool-chain (Keil, DS5 or GCC) can be chosen, the Prototyping kit makefiles uses only DS5.

    Is it possible to receive Prototyping kit makefiles that support tool-chain selection and in particular GCC?

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • Fail to run the compiled MPS2+ project

    elisorin
    elisorin

    Hi,

    After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.

    While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • What USB Blaster cable?

    urian
    urian

    Hello,

    I want to use an USB Blaster cable for rapid FPGA prototyping on the MPS2+. 

    The cables differ very much in price.  Is it recommended to buy an original Altera for over 200 Euro or can I use a cheaper nonamee one?

    Could you please recommend a cable…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • Cortex M0 Designstart missing/unknown files and ignored includes

    Berkay Uçkun
    Berkay Uçkun

    Hi everyone,

    I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • CM3 DesignStart Build warning messages with Quartus Prime 17.0.2

    TES
    TES

    Hi,

    I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

    I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

    Critical…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • Has anyone had problems with implementing App Note AN387 using Cortex M0 r2p0 on a Cortex-M + dev board?

    CraigS
    CraigS

    All,

    I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

    In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • Simulate Cortex-M0 FPGA implementation in ModelSim

    thexeno
    thexeno

    Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
    I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

    I tried to start with Linux to see if at least the "make" commands are working. Problem…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • DesignStart Eval on Terasic DE10-Standard Board

    ag4inst4ll0dds
    ag4inst4ll0dds

    Hello,

    For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
    The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

    If I try to compile the ".sof" file of the Eval package in Quartus Prime…

    • Answered
    • over 3 years ago
    • DesignStart
    • DesignStart forum
  • DesignStart Pro: APB on FPGA via Quartus Prime

    ag4inst4ll0dds
    ag4inst4ll0dds

    Hello,

    I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • arm cortex m3 designstart debug with st_link.

    chinaboy
    chinaboy

    I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

    I don't know how to solve the problem 

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • cortex M3 designstart can't read AHB peripheral register

    chinaboy
    chinaboy

    。。。

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • About V2M-MPS2+

    Bobby.zhou
    Bobby.zhou

    Hi,guys.

    We have already  applied for Cortex-M3 DesignStart Pro and purchased the V2M-MPS2+ motherboards.

    To my knowledge, V2M-MPS2+ motherboards was designed for DesighStart Eval and can be integrated with arm Embed OS easily.

    So, my question is:

    1, can…

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • how to implement mbed_blinky example on mps+2 board ?

    zhenyuliu
    zhenyuliu

    hi, GUys

       i buy a mps+2 board  and try to implement  mbed_blinky examples. but i meet issues on debugger and download axf files.

         now i can:

            1. export mbed_blinky examples for keil 

            2. compile success and generate axf file

            3. download fail

    …
    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • First compile, verilog files missing

    LeChuck
    LeChuck

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
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