Hi All,
i went through this link
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html
and related a53 vector table implementation.
in this regard, i have a question
1. Say a processor gets stuck in exception handler due…
Hi,
I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.
How to test:
GIC3.0:
1. read timestamp(t01)
2. core0 write ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)
3. isr in core1, read timestamp…
As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt.
I am a software engineer.
My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
This question related to the implementation of the instruction…
This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post.
This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post.
This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post.
Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.
I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30.
Actually I want to forward the interrupt from Distributor to multiple Cores but seems to use ITARGETSR, affinity…
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