Hello,

I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5.  My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation.  As part of our research, I have been tasked with…

Hi,

I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave? 

Would the the data be read from 0x100 only, with data[63:32] always…

address = 0x07 

transfer size = 32 bit

burst type  = INC

Burst length = 4 transfers

Can you please explain this example of unaligned word transfer on 64-bit bus.

Why the second transfer started at 8 and not from C?

i read the specification of AXI 4 protocol. i want to know what action will be performed by the master when it receive okay,exokay,slverr or decerr. okay and exokay says that the transfer is completed either by normal access and by the exclusive access…

In AXI4 Stream protocol apart from data byte two other byte types are defined known as position byte and null byte. 

For the position byte the description says: "A byte that indicates the relative positions of data bytes within the stream. This is a placeholder…

Hi,

In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

Hi ,

   What is the purpose of removing ID's (WID) in AXI4 ?

If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

I have one question for QoS with AXI4:

Can one master have multiple QoS values?

Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

Hi,

I'm getting two AXI4 protocol assertion errors.

For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

Is this a…

The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

"a read transaction can fetch more data than required"

To me, this can be interpreted in two ways:

1. The RVALID signal of the slave can be asserted for…

In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

Dear Forum,

Can you please confirm one thing.

When we have un-aligned transfer, do some of WDATA bits not used during that transfer?

For example, in the below unaligned transfer WDATA[7:0] are not used for the 1st transfer. Is my understanding right?

Hi Forum,

I cannot understand when address is being wrapped in WRAP burst.In my example, the WRAP condition never happens in other words, during BURST operation address always remains small than wrap address.

From the spec, the wrapping happens when

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

Eg. Burst length- Two , Burst size 16 bytes.

Please give me answers for different types of data bus width say for bus width …

Hi,

In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

Hello everyone,

I'm pretty new to axi and i still try to figure things out. I'm using Zybo device and created a custom ip with a master and a slave interfaces. I have create design as you can see in the below. Write transaction is work however, read transaction…

i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…