We are pleased to announce the release of the AMBA ATP Engine, an open-source implementation of AMBA ATP (Adaptive Traffic Profiles). The Engine significantly simplifies the adoption of AMBA ATP for workload modeling and accelerates the research and development…
AMBA AXI Write response
I am just going through the specs of AMBA AXI.
I've few questions.It will be great if anybody clarify
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
2) How to terminate…
I've few questions.It will be great if anybody clarify
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
2) How to terminate…
- over 6 years ago
- System
- SoC Design forum
applications of amba axi
Note: This was originally posted on 7th February 2007 at http://forums.arm.com
hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…
hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…
- over 6 years ago
- System
- SoC Design forum
AXI write strobes
Note: This was originally posted on 21st February 2007 at http://forums.arm.com
the AXI spec says:
the AXI spec says:
10.1 About unaligned transfers
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…
- over 6 years ago
- System
- SoC Design forum
Basics: C programming for ARM - AHB transfers
Note: This was originally posted on 18th September 2007 at http://forums.arm.com
Hello,
Would someone please help me about the next basic things?
I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…
Hello,
Would someone please help me about the next basic things?
I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…
- over 6 years ago
- System
- SoC Design forum
AXI Read/Write ordering
Note: This was originally posted on 24th October 2007 at http://forums.arm.com
Hello,
Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them. It then says that if a RAW dependency exists, the master must wait…
Hello,
Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them. It then says that if a RAW dependency exists, the master must wait…
- over 6 years ago
- System
- SoC Design forum
More AXI write/read ordering
Note: This was originally posted on 25th October 2007 at http://forums.arm.com
In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address. Sounds like the master's assumption upon…
In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address. Sounds like the master's assumption upon…
- over 6 years ago
- System
- SoC Design forum
AXI Cacheable vs. Bufferable
Note: This was originally posted on 19th November 2007 at http://forums.arm.com
If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…
If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…
- over 6 years ago
- System
- SoC Design forum
How to go from 32-bit to 64-bit AHB data bus
Note: This was originally posted on 21st November 2007 at http://forums.arm.com
Hi,
I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…
Hi,
I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…
- over 6 years ago
- System
- SoC Design forum
AXI protocol
Note: This was originally posted on 30th December 2007 at http://forums.arm.com
Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving in detail...as i`m very confused with these terms
Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving in detail...as i`m very confused with these terms
- over 6 years ago
- System
- SoC Design forum
Confusion over AMBA AHB hsize[] signal definition
Note: This was originally posted on 26th February 2008 at http://forums.arm.com
After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface. If an AHB bus is implemented…
After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface. If an AHB bus is implemented…
- over 6 years ago
- System
- SoC Design forum
AHB Multilayer
Note: This was originally posted on 30th April 2008 at http://forums.arm.com
In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…
In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…
- over 6 years ago
- System
- SoC Design forum
AXI locked access
Note: This was originally posted on 29th May 2008 at http://forums.arm.com
Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…
Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…
- over 6 years ago
- System
- SoC Design forum
AHB WRAP address boundaries
Note: This was originally posted on 18th June 2008 at http://forums.arm.com
AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…
AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…
- over 6 years ago
- System
- SoC Design forum
Wrap address usage?
Note: This was originally posted on 18th October 2008 at http://forums.arm.com
Hello guys..
I am working on AMBA AHB...
and came across the wrap address term...
Can you tell me that which kind of application need to do transfer using wrap address?
Hello guys..
I am working on AMBA AHB...
and came across the wrap address term...
Can you tell me that which kind of application need to do transfer using wrap address?
- over 6 years ago
- System
- SoC Design forum
questions about APB advantages
Note: This was originally posted on 8th November 2008 at http://forums.arm.com
Hi! dear all
Some APB advantages are listed in AMBA 2.0 spec. They are
"¢ performance is improved at high-frequency operation
"¢ performance is independent of…
Hi! dear all
Some APB advantages are listed in AMBA 2.0 spec. They are
"¢ performance is improved at high-frequency operation
"¢ performance is independent of…
- over 6 years ago
- System
- SoC Design forum
AHB Arbiter
Note: This was originally posted on 21st November 2008 at http://forums.arm.com
Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?
Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?
- over 6 years ago
- System
- SoC Design forum
AHB Busy states...
Note: This was originally posted on 24th November 2008 at http://forums.arm.com
Hello guys....
If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?…
Hello guys....
If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?…
- over 6 years ago
- System
- SoC Design forum
app crashes when compiled with OTime O3 using RVDS 4.0
Note: This was originally posted on 1st December 2008 at http://forums.arm.com
Hi,
I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.
My compiler…
Hi,
I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.
My compiler…
- over 6 years ago
- System
- SoC Design forum
AHB split retry response
Note: This was originally posted on 9th December 2008 at http://forums.arm.com
IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
has to to issue…
IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
has to to issue…
- over 6 years ago
- System
- SoC Design forum
AHB frequency
Note: This was originally posted on 6th January 2009 at http://forums.arm.com
Hi Friends,
My doubt is : what is the maximum AHB clock frequency ?
Regards,
P.Vignesh Prabhu
Hi Friends,
My doubt is : what is the maximum AHB clock frequency ?
Regards,
P.Vignesh Prabhu
- over 6 years ago
- System
- SoC Design forum
Bus Matrix
Note: This was originally posted on 28th January 2009 at http://forums.arm.com
What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
- over 6 years ago
- System
- SoC Design forum
PL031 verilog generation
Note: This was originally posted on 19th February 2009 at http://forums.arm.com
Pls, I need an answer to a blocking issue
I tried to generate a verilog code for PL031 connection matrix 2x3.
Unfortunely generated HSEL signal for each slave doesn't…
Pls, I need an answer to a blocking issue
I tried to generate a verilog code for PL031 connection matrix 2x3.
Unfortunely generated HSEL signal for each slave doesn't…
- over 6 years ago
- System
- SoC Design forum
the usage of WSTRB signal
Note: This was originally posted on 26th February 2009 at http://forums.arm.com
Hi All,
I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…
Hi All,
I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…
- over 6 years ago
- System
- SoC Design forum
ARM Cortex ICode, DCode, System buses
Note: This was originally posted on 26th February 2009 at http://forums.arm.com
I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
…I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
- over 6 years ago
- System
- SoC Design forum