In case of readunique transaction cache line is copied into the initiating master's cache(whether it is clean or dirty) and invalidated in snooped master's cache and then store operaation is performed in initiating master's cache line.

In…

I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.

Hi,

In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

Hi,

In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

Hi ,

   What is the purpose of removing ID's (WID) in AXI4 ?

If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

I have one question for QoS with AXI4:

Can one master have multiple QoS values?

Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

Hi,

I'm getting two AXI4 protocol assertion errors.

For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

Is this a…

The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

"a read transaction can fetch more data than required"

To me, this can be interpreted in two ways:

1. The RVALID signal of the slave can be asserted for…

i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

Could you please help me on this topics in AXI4 protocal ::

1. what is meant by Aligned and Unaligned address?

2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

Difference between axi_4 and axi4_alite?

Hi All ,

            Can anyone please tell the difference btw AXI3 and AXI4.

Regards

Muthuvenkatesh

hi,

what are the purpose of interconnect..?and why we nedd address routing table..in axi4

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

Eg. Burst length- Two , Burst size 16 bytes.

Please give me answers for different types of data bus width say for bus width …