Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?
what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.
This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…
Hi all,
I am new to protocols AHB and AXI.
can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?
Also what these boundaries are for? Does they represent the maximum slave size?
Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…
Hello,
I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.
1) I would like to know how read and write address requests issued…
i am not able to understand working of this CACHE signal pleas explain with simple example.
thank you!
Hi,
We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…
Hi,
In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.
My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…
Hi,
In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.
Now my question here is if the response is going to be ERROR(lets say SLVERR…
Hi,
In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.
But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…
In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :
The initiating master component requests a unique copy of the cache line…
Hi ,
What is the purpose of removing ID's (WID) in AXI4 ?
If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…
when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.
Background:
In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.
I am responsible for the board and FPGA design. Another software…
In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?
Hi,
I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:
- 32 bit data bus
- address x0001
- length 0 (1 beat)
- size 1 (2 byte)
My interpretation of the spec is that in…
