• Transfer size in AMBA AXI

    subhajit02
    subhajit02

    Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

    • over 2 years ago
    • System
    • Embedded forum
  • AXI-4 questions

    SBR_123
    SBR_123

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • AMBA AXI CACHE

    srp
    srp

    i am not able to understand working of this CACHE signal pleas explain with simple example.

    thank you!

    • over 2 years ago
    • System
    • Embedded forum
  • Burst Length of wrap type in AXI4

    KPranav
    KPranav

    As per spec, the burst length of wrap type should be 2,4,8 or 16. But at the same time it is also mentioned that burst length= AxLEN[7:0] +1, to accommodate the extended burst length of the INCR burst type in AXI4.

    If my burst length value is 2 i.e [00000010…

    • over 2 years ago
    • System
    • Embedded forum
  • Cache Maintenance Transactions

    Taniya Garg
    Taniya Garg

    Hi,

    I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?

    Can anyone please help?

    • over 1 year ago
    • System
    • Embedded forum
  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Etienne Alepins
    Etienne Alepins

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

    • over 1 year ago
    • System
    • Embedded forum
  • Problems about signal dependencies in AXI spec

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

    • over 1 year ago
    • System
    • Embedded forum
  • AXI read response in error case

    Anupam Jain
    Anupam Jain

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

    • over 1 year ago
    • System
    • Embedded forum
  • Why AXI4 changed the definition of AxCACHE?

    Yu-Hsin
    Yu-Hsin

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

    • over 1 year ago
    • System
    • Embedded forum
  • HREADY when no activity on bus

    Tushar Valu
    Tushar Valu

    Hello,

    We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

    ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

    So the questions…

    • over 1 year ago
    • System
    • Embedded forum
  • How to handle Cache flush in ACE?

    Taniya Garg
    Taniya Garg

    Hi,

    I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?

    Can anyone please help.

    Regards,

    Taniya Garg

    • over 1 year ago
    • System
    • Embedded forum
  • Store operations where the cache line is already cached (ACE protocol)

    Vedant2611
    Vedant2611

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

    • over 1 year ago
    • System
    • Embedded forum
  • Removal of WID's in AMBA AXI4

    mvenkatesh
    mvenkatesh

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

    • over 1 year ago
    • System
    • Embedded forum
  • SRAM for Cortex M0 -- Does It Need to Support Byte write?

    Ming
    Ming

    For the SRAM with Cortex M0, does it need to support byte write?

    What restrictions do I have with Cortex M0 if the SRAM only support 32-bit write?

    • over 6 years ago
    • System
    • SoC Design forum
  • How can I get IP-XACT descriptions of CMSDK components?

    Steven Dennis
    Steven Dennis

    We use IP-XACT based automation tools, mainly for register views, so need IP-XACT description of the APB registers for the CMSDK components.

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • AHB Slave HREADY

    VT
    VT

    Hello

    I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs.

    My question is Is there any specific condition for slave when it gives HREADY low?

    I am confused with HREADY signal that it is provided by the slave but at which…

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • AHB

    VT
    VT

    Hello,

    1.) Is it possible in real system that Master will send start address 0x01 ?

    If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?

    HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST…

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    Qiangsheng Xiang
    Qiangsheng Xiang

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • Configuration options for cxapbic for 32 masters and 2 slaves

    Sid
    Sid

    !

    Hi everyone,

    I am new to Amba Designer tool and ARM IP.

    Barely scratching surface.

    Recently I have been trying to create a config.xml file for cxapbic (Apb bus related interconnect) for 32 masters and 2 slaves.

    I realized that the 1st 4KB are reserved…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • why there is no split or retry responce in AXI ?

    Jay Zhao
    Jay Zhao

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • AXI narrow read with unaligned address

    jduarte
    jduarte

    Hi,

    I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

    - 32 bit data bus

    - address x0001

    - length 0 (1 beat)

    - size 1 (2 byte)

    My interpretation of the spec is that in…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • RMW operation on SRAM via AXI

    niket
    niket

    I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

    Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ?

    architt
    architt

    PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

    APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles…

    • over 3 years ago
    • System
    • SoC Design forum
  • AXI handshake between AW/AR-READY and B/R-RESP

    KalyanSuman
    KalyanSuman

    In AXI Write how the handshake between AW channel and B channel is taken care.

    Standard says that 

    "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

    Does that means BVALID will never be asserted in the same…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • How does QoS with priority and ordering allowed with AXI ID?

    tarun4682
    tarun4682

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

    • over 3 years ago
    • System
    • SoC Design forum
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