AMBA AHB

anvesh dangeti

1)what are the different generations in AMBA AHB?

Answered

2 months ago
System
SoC Design forum

AHB-Lite IDLE and hready related queries

Pavan_N

Hi,

Can someone clarify below queries I have wrt AHB-Lite,

Is there any relation between HTRANS=IDLE and hready ? Like,
1. Whenever IDLE comes hready is de-asserted (or)
2. Whenever hready is de-asserted, master gives IDLE
What is the maximum duration…

Answered

8 months ago
System
Embedded forum

Basics: C programming for ARM - AHB transfers

joewu joewu

Note: This was originally posted on 18th September 2007 at http://forums.arm.com

Hello,
Would someone please help me about the next basic things?
I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…

over 6 years ago
System
SoC Design forum

How to go from 32-bit to 64-bit AHB data bus

tamo tamo

Note: This was originally posted on 21st November 2007 at http://forums.arm.com

Hi,
I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…

over 6 years ago
System
SoC Design forum

Confusion over AMBA AHB hsize[] signal definition

davemac2 davemac2

Note: This was originally posted on 26th February 2008 at http://forums.arm.com

After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface. If an AHB bus is implemented…

over 6 years ago
System
SoC Design forum

AHB Multilayer

Jesuraj vinoth Joseph

Note: This was originally posted on 30th April 2008 at http://forums.arm.com

In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…

over 6 years ago
System
SoC Design forum

AHB WRAP address boundaries

myarm myarm

Note: This was originally posted on 18th June 2008 at http://forums.arm.com

AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…

over 6 years ago
System
SoC Design forum

AHB Arbiter

vishalrane vishalrane

Note: This was originally posted on 21st November 2008 at http://forums.arm.com

Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?

over 6 years ago
System
SoC Design forum

AHB Busy states...

LEO LEO

Note: This was originally posted on 24th November 2008 at http://forums.arm.com

Hello guys....

If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?…

over 6 years ago
System
SoC Design forum

app crashes when compiled with OTime O3 using RVDS 4.0

pradipig pradipig

Note: This was originally posted on 1st December 2008 at http://forums.arm.com

Hi,
I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.

My compiler…

over 6 years ago
System
SoC Design forum

AHB split retry response

abc_xyz pqr_def

Note: This was originally posted on 9th December 2008 at http://forums.arm.com

IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
has to to issue…

over 6 years ago
System
SoC Design forum

AHB frequency

vignesharm vignesharm

Note: This was originally posted on 6th January 2009 at http://forums.arm.com

Hi Friends,

My doubt is : what is the maximum AHB clock frequency ?

Regards,
P.Vignesh Prabhu

over 6 years ago
System
SoC Design forum

PL031 verilog generation

nicolan nicolan

Note: This was originally posted on 19th February 2009 at http://forums.arm.com

Pls, I need an answer to a blocking issue

I tried to generate a verilog code for PL031 connection matrix 2x3.
Unfortunely generated HSEL signal for each slave doesn't…

over 6 years ago
System
SoC Design forum

In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

Koteswara Rao P

Hi,

In AMBA AHB:-

For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

q) For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

Answered

over 4 years ago
System
SoC Design forum

AHB HREADY low not after address phase

Moish

What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

Thanks

Answered

over 3 years ago
System
SoC Design forum

Why the address boundary for AHB burst should not cross 1KB

Mohankumar

Why the address boundary for AHB burst should not cross 1KB??

And in case of burst operation, is that every beat the address increment taken care by master?

over 3 years ago
System
SoC Design forum

Regarding retry response

VIJAY KUMAR

Im new to the ahb protocol can any on give me an idea about retry response, when a retry response is generated from slave side.

Answered

over 1 year ago
System
SoC Design forum

Burst termination with BUSY transfer on AHB

Hyunkyu

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated.

But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length burst.

Doesn't it mean that INCR is not terminated?

…

Answered

over 1 year ago
System
SoC Design forum

AHB revisions from AHB3 to AHB5

Hyunkyu

I noticed that "Multi slave select" is one of the new features in AHB5.

But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?

I think we can do that with AHB3.

What is the major difference between AHB3…

Answered

over 1 year ago
System
SoC Design forum

AHB amba 5 lite - waited write transfer

michaels

Hello,

i didnt find at spec any note about the waited write transfer.

for example

T1 : NONSEQ + write transfer + HREADY is high

T2: HREADY dropped + HTRANS is idle - HWDATA ?

does the HWDATA have to be the right data or it can be any junk ? and only when…

over 1 year ago
System
Embedded forum

What is expected from response if in WRAP txn in AHB is un-aligned.

Spadhy

Hi,

In spec it's mentioned that in WRAP transaction the un-aligned address will be made aligned but only when it's crossing the boundary.

Wanted to know what's expected when the WRAP txn is started with a un-aligned address.

Case1: Starting…

Answered

over 1 year ago
System
SoC Design forum

What purpose do wrapping BURST transfers serve?

Kedhar Guhan

I've understood how it works and what happens in it, but what is the use of having a wrapping bursts? What are some scenarios where it provides an edge?

Answered

over 1 year ago
System
SoC Design forum

State Machine for AHB-Lite Protocol

Kedhar Guhan

This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor…

over 1 year ago
System
SoC Design forum

Why does an AHB slave require HBURST signal?

Kedhar Guhan

HBURST specifies the type of the transfer, but what exactly does the slave/(interface) do with the HBURST signal?

Answered

over 1 year ago
System
SoC Design forum

Can a simple processor with load-store architecture support BURST?

Kedhar Guhan

Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design…

Answered

over 1 year ago
System
SoC Design forum