• Security, the Fundamental Element in Next-Generation Networks

    Jim Wallace
    Jim Wallace

    Authors: Jim Wallace, Arm; Joseph Byrne, NXP

    It’s hard to imagine a day without relying on a computer or smartphone at work, when shopping or banking, chatting with friends, or even listening to music or watching a show. At the same time, it’s hard not…

    • over 2 years ago
    • Processors
    • Processors blog
  • Arm Technical Training – Any time, any place

    Matt_Rushton
    Matt_Rushton

    Partner Training at Arm has been a great success over the last 15 years. It has expanded the knowledge and capabilities of our Partners’ Engineering teams by delivering classroom sessions to over 4000 attendees in 2016 alone and has helped our Partners…

    • over 2 years ago
    • Processors
    • Processors blog
  • SMP to suspend an individual core with security OS

    astonelin@gmail.com
    astonelin@gmail.com

    Hi All,

    a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

    how to implement a suspend/resume flow on a individual core?

    TRM only mentions about how to clean cache and off-line from smp

    But how to do a cache flush through…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is eXecute-Only-Memory (XOM)?

    Joseph Yiu
    Joseph Yiu

    An introduction to eXecute-only-Memory

    eXecute-Only-Memory (XOM) is a firmware protection technique to help prevent 3rd parties from stealing or reverse engineering firmware, and at the same time allowing 3rd parties to add additional software to the…

    • over 3 years ago
    • Processors
    • Processors blog
  • What is meaning of Logical MMU ?

    Sahil
    Sahil

    Hi

    I have read in one of the ARM document for TrustZone that

    Within a TrustZone processor the hardware provides two virtual MMUs, one for each virtual processor. This enables each world to
    have a local set of translation tables, giving them independent…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The future of automotive is coming faster than you think

    Richard York
    Richard York

    As excitedly as we talk about it, you’d think the promise of fully autonomous vehicles is right around the bend, just another few miles and we’ll pull into our destination. In truth, we’re not there yet, and a few sceptics even suggest we’ll never get…

    • over 3 years ago
    • Processors
    • Processors blog
  • Embedded World Conference 2017 - Software Development in ARMv8-M Architecture

    Joseph Yiu
    Joseph Yiu

    This is a paper covering a introduction of software development on ARMv8-M architecture.

    Abstract

    The next generation of ARM® Cortex®-M processors, Cortex-M23 and Cortex-M33, based on the ARMv8-M architecture, introduce optimized TrustZone® security features…

    • ARM Cortex - session 11 - Yiu - Software Development in ARMv8-M Architecture.pdf
    • over 3 years ago
    • Processors
    • Processors blog
  • AM3352 TrustZone

    Roma B.
    Roma B.

    Hello,

    We want to develop complete IoT platform using  ARMmbed OS platform for an IoT application, based on TI's AM3352. Security and over the air firmware upgrade of another co-processor are of primary concern. As per our understanding, to build TrustZone…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-M - toolchains / virtual platforms

    Pierre
    Pierre

    Hello,

    I would be interested to try the new features of the ARMv8-M architecture, in particular v8-M TrustZone, but I can't find necessary tools in order to do so.

    1. I need a toolchain that supports the new instructions introduced with v8-M (SG, BXNS…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Secure world memory access with MMU disabled

    Zizhu
    Zizhu

    Hi,

    I am a newbie to the TrustZone architecture. I learned that, in secure world, whether a memory access is secure or not is determined by the NS field in the translation descriptor and, in non-secure world, the NS field will be ignored. I am wondering…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trustzone and Hardware virtualization support

    Justin
    Justin

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cannot access EL1 resources from EL3 or secure world on armv8.

    Tgn Yang
    Tgn Yang

    The working secerio is that I'm testing OP-TEE on a Hikey board(Cortex-A53, armv8), and they use arm-trusted-firmware(see https://github.com/linaro-swg/arm-trusted-firmware) to be the monitor running in EL3.

    I'm trying to access some resources in EL1…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A:TrustZone and MMU

    42Bastian
    42Bastian

    I wonder how VA->PA translation is handled from non-secure world with Aarch64.

    I see the HYP mode uses IPA so that the second stage translation may restrict the VM to certain memory.

    But what about limiting access to secure memory? Is it only possible…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • cross compiling the hello trust zone example

    Sean
    Sean

    Is it possible for me to cross compile the hello Trust Zone example referenced here: Cortex-A9 TrustZone example ? The build file contains the command options for the arm compiler. I do not have the board this example was meant for, and I am trying to…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM v8 secondary CPU bootup

    Harish G
    Harish G

    Hi experts,

         i am trying wakeup the secondary CPU core in bootloader, i am able to do this through a trusted firmware. The problem comes after wakeup!

    Once the cpu is up it will be in EL-2 mode and it executes a predefined function…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • why Interrupt 1023 (Spurious interrupt) happens when i set pagetable attribute on exynos5250?

    Yeo Reum Yun
    Yeo Reum Yun

    Hi, experts.

    I'm developing pagetable on exynos5250 and exynos5433.

    But i have very strange problem....

    when i mapping secure-memory-area as section with attributes that is

                   S = 1, TEX= 001, C =1, B = 1      =>  Outer and Inner Write-Back…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data abort, External abort.. How can i find cause????

    Yeo Reum Yun
    Yeo Reum Yun

    Hi, experts

    I'm developing Secure OS on A57/53 bit.LITTLE SoC. But as you know.. Cuz i'm really beginner..

    I beg your wisdom...

    Current situation is :

    • For making a TA. Bring the related data from REE and Mapping TEE side's NON-SECURE memory. (Data…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

    Yeo Reum Yun
    Yeo Reum Yun

    Hi Experts,

    I'm reading white paper for ARMv7 and ARMv8.

    but when i reading cache part and memory re-ordering, i have silly questions.....

    Suppose there are below instructions..

     

    Core A:

         STR R0, [Msg]

         STR R1, [Something…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to set inner of outer shareability on page table entry WITHOUT TEX remap??

    Yeo Reum Yun
    Yeo Reum Yun

    At first, sorry to my fool English.

    I want to know how to set to inner or outer shareable attribute on page table entry using TEX, C, B and  S bit (without TEX remap).

    I knew if i use TEX remap, the PRRR NOT bit used to set to outer or inner but i…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How can we boot linux kernel in ARM FVP w/ TrustZone?

    Yoshiharu Imamoto
    Yoshiharu Imamoto

    Hello, everyone.

    Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).

    I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which

    kernel to run in the secure world, but am sure to run Linux in Normal…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to schedule Secure/Normal kernels in TrustZone implementation?

    Kaiyuan
    Kaiyuan

    I read TZ whitepaper. TZ's software architecture includes normal OS, secure OS, and a monitor that manages switching between two OS. The notion is clear. But how to implement them confuses me.

    Running and managing two kernels on a SoC needs mechanism…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 initialization code & TrustZone/ Secure Boot

    Vincent Siles
    Vincent Siles

    Hi,

    I just got a raspberry pi 2 and I'd like to play with Trustzone.

    People on the Raspberry forum http://www.raspberrypi.org/forums/viewtopic.php?p=697474#p697474 explained me how to

    get my hand on the boot of the 4 core A7 CPU, and I managed to boot…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trust Zone on Raspberry Pi unexpected behaviour?

    Vamsi Krishna Atluri
    Vamsi Krishna Atluri

    I am working on the trust zone extension on raspberry pi B+ which has the ARM1176JZF-S processor. According to given documentation on arm11, there will be 3 exception vector tables each for Secure world, Non-secure(NS) world and monitor mode resp. And…

    • Answered
    • over 6 years ago
    • Processors
    • Classic processors forum
  • What will I get if I try to access SCR in cp15 when my core is in non secure mode.

    Jay Zhao
    Jay Zhao

    I know that when the core is in non secure mode (non TZ), the normal world software is not able to access SCR in cp15.

    But I'm wondering what consequence it will cause if such operations occur.

    Unexpected results and the core runaway or the operations…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What will I get if I operate p15 to switch to TZ mode when I'm right in TZ mode.

    Jay Zhao
    Jay Zhao

    As above~

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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