Hi,

If an interrupt occurs when in Thumb state, does the LSB of the link register become 1.

Thanks,

Revanth

Hi !

I am writing assembly code for some ARMv7a and ARMv8a CPU. I know that code has to be 4 bytes aligned, but I saw in several places (uboot/linux) the ".align 4" GCC directive, which will align to 2**4 = 16 bytes.

When writing code that will…

I've been reading books on the ARM Cortex-M architecture and as already mentioned in other post, all the books are consistent in saying that the PC points four bytes (Thumb Instruction Set) forward due to Pipeline (prefetch).

Did some testing with…

Hi,

I'm somewhat confused with the Thumb mode code size.  My understanding is compiling with ARM mode will generate 32-bit instructions and compiling with Thumb mode will generate 16-bit instructions.  When I compile my Cortex-M0+ project (which should…

Hi,

I am learning ARM assembly code. The following is a Thumb disassembly from a short .c file:

int main()

{

      printf("Hardware test, finish testing.\n");

      return 0;

}

00000000 <main>:…

Any idea about instructions marked as UNPREDICTABLE: can it then be UNDEFINED?

In other words: UNDEFINED REQUIRES the instruction to cause UND-exception, but

MAY UNPREDICTABLE do that, or does it have to execute normally except that the result may be…

Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?

I didn't find anything different from the basic ADD  (register) and SUB (register) except the documentation:

<Rd> The destination register…

From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?

Is there some signal bit represent the code is ARM or Thumb code, this is just my guess.

Hi,

When I read the words below dot line, I don't understand why "R14 is adjusted

to allow for the prefetch"

Could you explain it to me?

Thanks,

.......

Branch with Link (BL) writes the old PC into the link register (R14) of the

current…

Hi,

Hi,

When I read the following on ARM website, I don't understand the first line. When I change ITTE to TE (as 'IT can be omitted"), the assembler complains an error of this line.

Could you explain it to me?

Thanks,

  ITTE NE ; IT can be omit…

Hi,

I find the following code snippet online on ARM state change. Although that whole material looks solid, the second line in the blue code below is puzzling.

add R1,PC,#1 ;Load address of SUB_BRANCH, Set for THUMB by adding 1

I don't see how the above…

Hi !

We are writing an OS targeting 32 bits ARM platform, where binaries can be compiled in ARM or in Thumb mode.

At the moment, to execute a new process, I load the info from an ELF, set lr_usr to the entry point address, set spsr_usr to a default value…

Dear colleagues.

I am compiling the Intel TBB in an effort to optimize my code to the Cortex-M53, however, because I was still forced to use GCC 4.9 I'm getting some warning messages about the use of  32bit Thumb Instrucions in IT blocks:

Warning…

Hi,

When I read about Thumb2 instructions, I have such a question: How many states for a Coretx A8? I know it has ARM and Thumb states. Thumb2 instruction is belong to Thumb state? Then does A8 have a pure Thumb instruction besides Thumb2 set?

Thanks,