• Disabling PFU / instruction pre-fetch on Cortex-R4?

    N. Gineer
    N. Gineer

    Hello,

    I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me:

    Determines if instructions can be cached at any available cache level:
    0 = instruction…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Cortex-R5: Data abort handling

    c0deface
    c0deface

    This may sound stupid but I'd like to confirm my understanding of the processor behavior, in the event of a Data Abort. Section 3.8 of the Cortex R5 Techincal Reference Manual explains the Exception handling by the processor and my current understanding…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • efficient c programming

    Wenchuan2018
    Wenchuan2018

    Hi everyone,

    I wonder if there is a documentation that explain how to program efficiently on arm cortex-m and arm cortex-r platform?

    I found "arm system developer's guide", but i worried it was too "old-fashion" because it only contained upto armv6..…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can we inspect contents of the return stack to get the call tree?

    Etienne Alepins
    Etienne Alepins

    Using Cortex-R5F, I would like to get the contents of the 4-entry call-return stack (i.e. get the addresses). Is this possible through some indirect manner?

    The goal here is to have the knowlege of the call tree above the current execution point (backtrace…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Porting FreeRTOS On R-52 Cortex

    Himanshu Khanna
    Himanshu Khanna

    Hi Experts,

    I need to run freeRTOS on processor having Arm cortex -R52 series .I have download source code from freertos.org for ARM_CR5 series.Does all port file will be compatible for R52 processor also and if no what are the changes we need to make…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Hypervisor Mode to System Mode in R52 cortex

    Himanshu Khanna
    Himanshu Khanna

    Hi Expert,

    I am using processor with R52 Arm cortex and I need to change  hypervisor mode to system mode during run time i.e EL2 to EL1.Is there any instruction to change this?

    Thanks In Advance.

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Is Advanced-SIMD supported in Cortex-R5F?

    Etienne Alepins
    Etienne Alepins

    Hi,

    I have a Cortex-R5F core in which integration register value CPACR.ASEDIS = 1 and CPACR.D32DIS = 1m which says Advanced SIMD is not available. However, in ARM Cortex-R5F Technical Reference Manual revision r1p2, §2.1.2 "ARM architecture", it says…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • When is Cortex-R5 Virtual Peripheral AXI bus used?

    Etienne Alepins
    Etienne Alepins

    The Cortex-R5 has a single AXI peripheral physical bus which is divided into a LLPP Normal AXI interface and an LLPP Virtual AXI interface. The TRM document also explains that ordering is disconnected between these 2 interfaces. Fine.

    However, I am not…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Cache ECC in Cortex-R5 & Event bus

    Gael
    Gael

    Hi everybody,

    I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery".

    As far as I understand, in that mode, as the memory…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence

    Sandeep Bobba
    Sandeep Bobba

    Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip.

    so far we were using the concept of software based cache coherency mechanism to communicate between R5 and A53 worlds…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-R / R-Profile forum
  • Between R or A Family... ?

    Jerome Decamps - 杜尚杰
    Jerome Decamps - 杜尚杰

    Hi,

    Can you give me a concrete example of an application requiring the cortex-R family (exept for the watch and the video-recording).
    Given the gap in price between processors,  Except in the case of a large-scale purchase why not choose the cortex-A family…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • IOC flag at FPSCR register

    hotta
    hotta

    I using Cortex-R4.

    And I reading "Cortex™-R4 and Cortex-R4F Technical Reference Manual(Revision:r1p3)".

    In my system,  IOC flag in FPSCR register is set with unexpected processing.

    What is the condition of set IOC flag in FPSCR register…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Does Cortex R4x support SPI?

    Anurag_Kumar
    Anurag_Kumar

    I am using IWR1642, which is based on Cortex R4X from Texas Instruments.

    It states it has 2 SPI, but I can't seem to find any headstart in R4x datasheet.

    Any help would be really appreciated.

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • PMU Register description is not clear in Arm Cortex -R52 Processor Revision: r1p1

    Reco
    Reco

    Hi ,

    I am NXP working for functional validation group and writing PMU API but facing issue for detailed description of many of the PMU registers .

    I am referring to "Arm® Cortex®-R52 Processor Revision: r1p1".Many places UNK is written for reset values…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • The path to 1.5 billion 5G-ready smartphone devices

    Jack Melling
    Jack Melling

    Every 10 years mobile connectivity has a generational evolution. We’ve had 1G (voice calls), 2G (SMS messaging), 3G (web browsing) and 4G (LTE/ rich internet services). We’re now reaching the 5G evolution, which, like the other four phases of connectivity…

    • over 1 year ago
    • Processors
    • Processors blog
  • I am very new to ARM, still understanding the terminologies. What is the difference b/w the Cortex family and the x-gene?

    Moix
    Moix

    Where can i get a list of all these family of ARM processors and their differences

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to get started with ARM cortex R series programming?

    PraveenMax
    PraveenMax

    Hello All,

            I am proficient in C language and also been doing linux based developments on ARM cortex A series SBCs so far.  But now I am interested in programming the Cortex-R series processors for various real time projects. Please guide me in the following…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

    Kun.Niu
    Kun.Niu

    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • which processors are very advanced processors

    karthi
    karthi

    i just want to know which processors are very advanced processors in  cortex-A,R and M series.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to test " Lock-Step " is working on Cortex-R5 ?

    Ravinder
    Ravinder

    Dear Forum,

    How to test " Lock-Step " is working on Cortex-R5?

    Please provide inputs on Testing this feature.

    Thanks,

    Ravinder Are

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Lock-Step mode execution on Cortex-R5

    Ravinder
    Ravinder

    Dear Forum,

    Could some one please elaborate on ,

    1. what is Lock-Step Mode ?

    2. What is the General HW configuration required ?

    3. How to make a program/application executable in Lock-Step mode ?

    - In Cortex-R5 , what are all compared at every state ? all…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Why Cortex-R series is real time oriented ?

    Ravinder
    Ravinder

    Hi Forum,

    Why Cortex-R series is real time oriented than other ISA(ARM/others) ?

    Is there a list of all the points and comparison with ARM Cortex-A ?

    Why we can not make Cortex-A to suite for real time, which brings to think of Cortex-R ?

    I am trying to understand…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex-R4F Re-entrant Example

    Taylor Hillegeist
    Taylor Hillegeist

    I was reading a post regarding re-entrant interrupts where you said:

    Re: Is there ANY Cortex core that supports reentrant interrupts?


    Hi Marcus, Cortex-R and Cortex-A processors does not have NVIC. Users (SoC designers) using these processors can use…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which ARM core is best suited for DSP applications?

    Gaurav
    Gaurav

    Hi,

    I am starting work on a project that would require a processor to interact with a custom chip that we have designed and also with a robotic arm. The processor will be programmed to control the robotic arm based on the inputs from the custom chip. The…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which instruction format does Cortex-R support,encoding A1 orA2?

    fanfanll1984
    fanfanll1984

    I see it support encoding T2 for Thumb-2 instruction set.But which instruction format does Cortex-R support for ARM instruction,encoding A1 orA2?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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