• When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to properly measure sleep time with DWT?

    Tilen
    Tilen

    Hello everyone,

    I need to measure sleep time of my Cortex-M4 processor (STM32F4xx).

    I looked at DWT where I also use normal tick counter and I enabled SLEEPCNT counter.

    However, I noticed that it is 8-bit register with event generation support.

    Now, there…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Prefetch Abort in Cortex M processors

    kmdinesh
    kmdinesh

    Hi,

    We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify the corresponding address. In Cortex R5, we are taking…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • A panic function to halt the processor in low-power sleep using WFI?

    Alexei
    Alexei

    As part of fault detection / debugging, it's useful to have a panic() function that halts the processor.

    It is easy enough to disable interrupts and put the processor in an infinite busy loop (while (1)). However, that burns power, and I am looking…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DWT

    Gabor M.
    Gabor M.

    Hello,

    I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M register RAM and Flash periodical check?

    Half past nine
    Half past nine

    Hi ARM,

    How to check Cortex-M4 register,RAM and Flash periodically using software when the processor is running?

    Best regards,

    Frank

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What's happening if NMI is active (via a push-button) during µC (Cortex M4) start-up (power on)?

    Aurelien
    Aurelien

    Hi everyone,

    I need help about NMI that seems to freeze mu µC during power on.

    I use a cortex M4 ( K64 from NXP/Freescale ). On the board I use, the NMI is connected to a push button.

    If I don't press the NMI button, my software run.

    If I press…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Linker in gnu arm toolchain says "group ended without start" thought there is no such option in my build

    ShyamThella
    ShyamThella

    shyam@shyam:~/projects/zynq/microzed/linux_source/Test_Chips$ make
    make -C  /home/shyam/projects/zynq/microzed/linux_source/Test_Chips/../dev_tools/build
    make[1]: Entering directory `/home/shyam/projects/zynq/microzed/linux_source/dev_tools/build'
    Making…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • undefined reference to `atan2'

    Former Member
    Former Member

    Hi Friends ,

    I need to fix this problem and I've read something about gcc but I didnt understand how can I do it.

    [cc] C:\Users\Emrah\Desktop\imu_STM32F407\imu\Src/main.c:39: undefined reference to `atan2'
    [cc] collect2.exe: error: ld returned…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cache attribute write back/write allocate for Cortex-M4

    nothing
    nothing

    What is different between write back with write allocate and write with non write allocate on Cortex-M4.

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Blink Newbie help debug!

    Ole
    Ole

    Hi Forum.

    I'm new to ARM, but have experience with AVR. I'm just trying to make a Hello World with blinky LEDs. I have this board:

    https://forum.micropython.org/viewtopic.php?t=3086

    So ok, everything seems to be setup right. I can compile and…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hard Faults and MemManage Faults in Cortex m3/m4

    Muzahir
    Muzahir

    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated. But in my case hardfault is also not triggering.

    Here…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MPU

    Vivek_yadav
    Vivek_yadav

    Hi

    Using STM32f4 Board, I am enabling MPU in between any code (simple program) always causing memory management fault on debugging fault that (

    IACCVIOL) bit is set, It means 

    • Attempting to execute an instruction from a memory region marked as…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interfacing FRDM-K64F with Camera module

    Shwetakr
    Shwetakr

    Hi Team,

    How can we interface FRDM-K64F kit with camera module?

    Thanks & Regards,

    Shweta

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Measuring Cortex-M4 instruction clock cycle counts

    Dan Lewis
    Dan Lewis

    I'm trying to find a reliable method for measuring instruction clock cycles on the STM32F429 MCU that incorporates a Cortex-M4 processor. Part of the challenge is that although the core CPU has no cache, ST added their own proprietary ART Accelerator…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How does Cortex-m4 core interact with other master devices?

    William Wong
    William Wong

    How does Cortex-m4 interacts with other master devices such as DMA while m4 core does not have Hbusreq and Hgrant ports? m4 core does not have interfaces to arbiter.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Raising priority of PendSV within NVIC when PendSV pending

    Ramzyo
    Ramzyo

    Hi,

    I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,

    1) High priority interrupt ISR is…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interruptible Instructions on Cortex-M4

    praffeck
    praffeck

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • LDREX/STREX on the M3,M4,M7

    Trampas
    Trampas

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to prepare ADC data for Q31_t CMSIS DSP functions?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've another post on the forum (here's the link Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? ), but since I think I made some small steps forward I felt I could be a little more specific. I hope this…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • what situation will the FPCA in Cortex-M4 change?

    ctc8631
    ctc8631

    Hi all,

    I'm study Cortex-M4 recently, and try to use floating point calculation,

    I read the book about that saying FPCA in control register will be set 1 after FPU work,

    but I'm not sure that when will FPCA be changed after set 1, or it will never…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

    marcusob
    marcusob

    Hi,

    I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    MSaif
    MSaif

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 - Returning from Interrupt

    marcusob
    marcusob

    Hi,

    I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get the ISR handler hit, but after I perform my ISR function…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • An algorithm on a M7 is slower than on M4 - why?

    Muragavino
    Muragavino

    Hi there,

    we are working on an audio project, where we move some firmware from an STM32F407 (ARM Cortex M4) to an ATSAME70 (ARM Cortex M7). Despite the ATSAME70 runing at 300 MHz, while the STM32F407 runs at only 168 MHz, the ATSAME70 is definitely slower…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
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