• 【Cortex-M4 with STM32F412RG】

    Kieron Kotaroh Nakamura
    Kieron Kotaroh Nakamura

    I am now composing functions to wake up Cortex-M4 with STM32F412RG embedded on Arduino using timers after making Cortex-M4 deep sleep mode.

    In realising the functionality above, peripheral clocks should be operated by some sources, Since deep sleep mode…

    • Answered
    • 5 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • Understanding Linker Map function addresses for Thumb code in Keil uVision

    Michael Hul
    Michael Hul

    So this seems like a pretty simple question, but I have not been able to find a clear answer. 

    I understand that function pointers with the LSB of the address set indicate that the function is in Thumb mode (https://www.keil.com/support/docs/3133.htm)…

    • 20 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the execution priority inside WFI for CortexM4?

    Jayden Huang
    Jayden Huang

    Hi,

    We always have the following code to make sure that only the interrupts with higher priority than 0x20 will wake up the processor.

    PRIMASK = 1
    
    BASEPRI = 0x20
    
    do sth...
    
    WFI()
    
    do sth...
    
    PRIMASK = 0

    But I think if we’re in the critical…

    • 22 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • Debug single step and interrupts not executing

    KjO
    KjO

    I am trying to track down a hard to find issue on a Cortex-M4. Leading to a lot of single stepping.

    I have noticed that the CPU does not seem to process interrupts as expected when single stepping.

    E.g.

    Currently the CPU core has PRIMASK = 0 and ICSR…

    • 1 month ago
    • Processors
    • Cortex-M / M-Profile forum
  • Processor always jumps to default exception handler

    m3taw1lL
    m3taw1lL

    Good day,

    My code for configuring the NVIC and peripheral interrupts are already working as expected, but the only problem now is the debugger shows that the processor always jumps to the default handler (__default_handler) and never on my defined interrupt…

    • Answered
    • 2 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • stmdb instruction *appears* not to work correctly - Cortex M4 / SAM4L

    HarryAtElpro
    HarryAtElpro

    I'm struggling to track down a problem here. It appears to be that the stmdb instruction isn't pushing all of the requested registers, and when the corresponding ldmia.w instruction executes, it pops a PC value that sends the processor executing code…

    • Answered
    • 2 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Compiling libgcc not optimized

    EnricoTabanelli
    EnricoTabanelli

    Good moorning,

    I am trying to compile libgcc for arm-none-eabi target from scratch, since I need to compare Floating Point SW emulation on an ARM Cortex-M4 and Risc-V based processors. The problem is that by default GCC includes the optimized version…

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to realise Real-time detection of access of memory beyond the bounds of an allocation block, instead of period detection in Cortex-M4. Please give me any idea.

    Gray
    Gray

    In my application, I have already redefine malloc and free with keil. Now I hope that the program
    will be stopped immediately at the exact location at which the program wrote beyond the
    allocated data.

    Is there any idea to achieve it?

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • CMSIS5: Matrix assignment doesn't work in my code. How to debug?

    Guglie
    Guglie

    Matrix assignment doesn't work in my code, seems a very strange bug, probably in my code, but how can I debug?

    I tested with CMSIS 5.6 and 5.7

    arm_matrix_instance_f32 Hm;
    static float H[3] = {0}; 
    arm_mat_init_f32(&Hm, 1, 3, (float *)H);
    …
    • 4 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Which bit fields are for Cortex-M4F SCB_ICSR.VECTORPENDING

    JL.Zhang
    JL.Zhang

    Hi Team,

    I would like to check the SCB_ICSR register, the content of 'Cortex-M4 Devices Generic User Guide' makes me confused. 

    According to the document DUI0553B, this figure shows the VECTORPENDING bit is [21:12]. But the Table 4-15 shows that…

    • 6 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Reading analog pin while boundary scanning

    ronit
    ronit

    Hii everyone,

    I'm just starting to boundary scanning methods. After seeing a diagram in one of your blog, I come to know that there is a scan cell between register and actual pin, from where we can see the state of a pin whether it is high or low by checking…

    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Reading suggestions to start programming with STM32H747 like mcu, especially with GCC

    Carlos Delfino
    Carlos Delfino

    I'm starting my studies on programming for Single Chip MCU with multicore, and I'm having a little trouble finding material on this topic.

    I read a post here in the community about the NXP's LPC4300 which is a Cortex-M4 + M0, which was very instructive…

    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem when dynamically loading code (Cortex-M4)

    Mrat
    Mrat

    Hello everyone.

    I want to implement dynamic loading of functions in RAM for a Cortex-M4.  It partially works but with a small hack which is not ideal.

    First I create the binary data for the function by compiling my desired function:

    int f1(int a,int b)…

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • GSM driver in Arm Cortex-M4F

    vinoth
    vinoth

    Hi All,

    I needs to port GSM driver in Cortex M4 Core. I am working on IMX8QM have Cortex-M4 Core. Will you please provide the GSM driver ?

    Regards,

    VinothS,

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • FPB BreakPoint(without Debugger)

    shincm
    shincm

    Hello,
    My App (cortex m4) needs to set up a breakpoint directly from code, in order to jump to an interrupt when an instruction from a certain address is fetched.
    This without using a debugger.
    I searched in the forum and tried the method.

    1. DebugMon…

    • Answered
    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Example of what happpens inside the Cortex-M 4

    Frederikke Kold
    Frederikke Kold

    Hello i am a student at cphbusiness in Denmark, and i am currently doing a research project on the Cortex-m 4. 
    i am hoping someone can help me understand what exactly is going on inside the processor. I have attached a picture, and i am hoping someone…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • STM32H745 dual-core debugging with IAR toolchain

    madhan719
    madhan719

    Hi All!

     

    I am working on STM32H745 dual-core controller and IAR Embedded Workbench for ARM toolchain V8.40.1 for development.

    I have completed all my work on individual core test and debugging with help of ST-Link V3 as debugger but unfortunately, I am…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Performance ratio between A35 and M4

    Mohamed_Tarek
    Mohamed_Tarek

    I am working on project and i used A35 to measure the performance of Application and this application will be ported on M4 , is there a fixed ratio or an equation so i can estimate the execution time of the application on CM4 ?

    • Answered
    • 10 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Timer interrupts synchronization in Cortex M4

    satheesh21
    satheesh21

    Hi,

    I am working on Cortex M4 based Microcontroller.

    I have one timer(TIM0) running and when it gets restarted, GPIO pin is set. I have one more timer (TIM1) running separately and it sets another GPIO pin.

    Now I would like to synchronize these two timer…

    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)

    schroedingers_katze
    schroedingers_katze

    I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.

    In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region…

    • Answered
    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • system reset request (NVIC_systemreset) does not restart the M4 controller

    satheesh21
    satheesh21

    Hi,

    I am working on M4 microcontroller. I would like to perform soft reset of the system. so I have used NVIC_SystemReset function as shown below


    __STATIC_INLINE void __NVIC_SystemReset(void)
    {
      __DSB();                                            …

    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 and ARM FIR Q15 Hardfault

    KoRba
    KoRba

    Hi

    I have tried to test CMSIS DSP FIR library in my STM32G474. Unfortunately after writing a simple test code, where i have prepared input signal and fir coefficients (by Matlab, verified) processor after executing arm_fir_q15 instruction goes to the…

    • Answered
    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • gcc does not generate correct code while building PIC

    rgujju
    rgujju

    Hey guys,

    I have been exploring building PIC using the gcc toolchain and I think there is a bug.

    I first build a shared library using 

    arm-none-eabi-gcc -shared -mcpu=cortex-m4 -mthumb -Wall -g -fPIC -fmessage-length=0 --specs=nosys.specs mylib.c -o libmylib…

    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cannot access Memory (@ 0xe000edf0, Read, Acc Size: 4 Byte)

    c m
    c m

    Hi guys,

    I have been developing a LPC54616J512 (Cortex-M4) with a ULINKpro, however I changed some build settings and now I get the following message:

    Cannot access Memory (@ 0xe000edf0, Read, Acc Size: 4 Byte)

    I have reverted my code and build settings…

    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • IT instruction block question : how does this work .. (block seems always executed)

    d.ry
    d.ry

    I have this 'tight' piece of ASM I'm looking at how it's working, and it contains IT instruction ( I've never seen before until now).

    Now all code works (compiler generated!) , but, i'm also stepping though each instruction for cycle…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
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