• "Dormant Mode" for Cortex M3/M4

    Steven Dennis
    Steven Dennis

    Hi,

    We are interested in minimizing startup time from deep sleep mode.

    Some of the older ARM cores implement a dormant mode whereby the CPU core context (state) is written to RAM prior powering it down, and then then restored after the CPU core  is powered…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • about tail chaning of Cortex-M0

    下田敏郎
    下田敏郎

    Hello.

    I'm studying about the tail chaining of Cortex-M0.

    Is it same as Cortex-M3 or M4?

    Best regards.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • cmsis NVIC question.

    Setianian
    Setianian

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Race condition between wake up event and WFI on Cortex-M3/M4

    neo
    neo

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How long bitfields on which ARM?

    Øyvind Teig
    Øyvind Teig

    I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

    Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Help me jump into ARM world !(I know nothing but AVR)

    kamran
    kamran

    Hi,  Sorry if this is a long thread but i'm really confused.

    I program for AVR MCUs and also know about Arduino, I can program for different ATMEL MCUs with looking at datasheets, And i also programmed a few basic stuff on Cortex-M3 LPC1768, without…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Break Points and Watch Points

    harshan
    harshan

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Where to find the execution cycles of Cortex m7 instruction

    tyskin
    tyskin

    for Cortex-M0, M3 and M4, I can find the execution time in their Technical Reference Manual > Programmers Model > Instruction set summary 里面查看

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/CHDCICDF.html

    but for M7 It said that…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When will be the Release of "The Definitive Guide to Cortex M7" ??

    harshan
    harshan

    Hi Sir,

    may be the title of this question looks fun, but i am eagerly waiting for your next book "The Definitive Guide to Cortex M7" are you working on this book?? When could i Expect this book

    Thanks and Regards,

    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How cortex-M4 handles data hazard situations in the pipeline?

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

    Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.

    Is the processor also use the method of "Forwarding" in order to handle…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Forced Hardfault (INVPC) Exception Error

    Lokesh
    Lokesh

    Using ARM coretx-M chip set

    Getting random  INVPC hard fault exception error, while running iperf tool for measuring n/w throughput.

    Hard fault reg: 0x40000000

    xPSR: 0x01000000

    PRIMASK: 0x00000001

    CONTROL: 0x00000000

    Please help to find the possible root…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    Trampas
    Trampas

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interruptible Instructions on Cortex-M4

    praffeck
    praffeck

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hard Faults and MemManage Faults in Cortex m3/m4

    Muzahir
    Muzahir

    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated. But in my case hardfault is also not triggering.

    Here…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • LDREX/STREX on the M3,M4,M7

    Trampas
    Trampas

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    MSaif
    MSaif

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MPU is not triggering MemFault or HardFault

    Muzahir
    Muzahir

    MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location, MPU does not trigger fault.

    Here's a code…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Question about the Pipeline, clock cycle and machine cycle in Cortex-M Series.

    tyskin
    tyskin

    Recently I'm learning the implement of ARM cortex m core in order to optimize my software to be more efficient and be easier to predict its execute time. But now I'm confused about the clock cycle, machine cycle and the pipeline of cortex-m.

    …
    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit)

    harshan
    harshan

    Hi Sir,

             Can i change Flash Memory Permission through MPU??

    Thanks and Regards,
    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Get current active interrupt priority

    Jonathan Weber
    Jonathan Weber

    Hi everybody,

    We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.

    In our implementation we need to determine…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • 'Sort and Count' program using Cortex-M3 Assembly (or less preferably in C language)

    Vickey Khan
    Vickey Khan

    Construct the following null terminated string in code area (i. e. in ROM)

    str         DCB       “p1er3fec6tst1r2an5ge7rs8”.0

    Write an assembly program that will count and…

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [C++11][Cortex-M] - distortos - object-oriented C++ RTOS for microcontrollers

    Freddie Chopin
    Freddie Chopin

    Hello!

    I finally decided to share some info about a project I've been doing for the past 8 months. Currently it can be considered "alpha" or maybe "early beta" stage, but - despite literal meaning of these terms - the things that are already done (and…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARM Cortex-M3/M4 Toolchain and IDE

    Guy Dillen
    Guy Dillen

    Hi,

    I would like setting-up a ARM GCC Toolchain + IDE for developing for my Cortex-M3/M4 Processors (more types of cortex processors would be a plus). I downloaded GNU Tools for ARM Embedded Processors GCC ARM Embedded in Launchpad. What else do I need…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-M3 or -M4: Which is better?

    Velagala J R N D V Reddy
    Velagala J R N D V Reddy

    Hi,

    I need some clarification about which one is better either Cortex-M3 or -M4. Which one is present trending and which one having good future.

    Thanks in advance.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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