• NVIC and ARM asm

    martin
    martin

    Cannot configure interupts of TIM6 on stm32f103 board

    Does my NVIC configuration wrong?

    Code:

    @ stm32f103 timer & interrupt test by laper_s (from 2019-02-02)
    
    .thumb
    .cpu cortex-m3
    .syntax unified
    
    .word   0x20005000
    .word   start + 1
    
    b   start…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • CortexM3

    Khushi
    Khushi

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • LDREX/STREX on the M3,M4,M7

    Trampas
    Trampas

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Documents have release Notes or update history?

    MR.Smile
    MR.Smile

    The G version has 410 pages!

    However, the H version reduce to 133 pages!

    It's like a big lost! 

    what's difference between the older and newer version?

    I think it's the ARM job to tell the difference. It's hard and wasting time for the user to…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    MSaif
    MSaif

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interrupt switching during Late Arrival- CortexM3

    Vartika Singh
    Vartika Singh

    In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't need to do any state saving. What does it mean by …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to start accessing the flash rom on Cortex-M3 design kit by JTAG?

    ele
    ele

    Hi,

    I'm trying to simulate which is accessing the flash rom on Cortex m3 design kit by JTAG?

    Is there any related test case or example?

    How to start accessing the flash rom on Cortex-M3 design kit by JTAG?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Store the value of PC to Memory address

    Muzahir
    Muzahir

    I want to store the value of Program Counter(pc) to a memory location.

    I did this, 

        LDR R1, =[0x20000000]

        STR R15, [R1,#0]

    I got an error saying, "Error: r15(pc) not allowed here -- `str R15,[R1,#0]'.

    How should I get over this error?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MPU is not triggering MemFault or HardFault

    Muzahir
    Muzahir

    MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location, MPU does not trigger fault.

    Here's a code…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • pre emption of the interrupts in the cortex m3 arm v7

    sana srikar
    sana srikar

    i am a beginner in this subject and i started reading the TRM from the infocenter

    one thing confused me

    Interrupt grouping    in this link it is written as

    "Only the group priority determines preemption of interrupt exceptions. When the processor is executing…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does matrix4x2 implement in busmatrix?

    ele
    ele

    Hi,

    Currently I'm digging the bus matrix 4x2 bus matrix from 

    But I have some question.

    How does the bus matrix4x2 implement in bus matrix?

    I just draw what I've understand it as the below

    Am I understanding correctly?

    I want to understand internal…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How does memory work in cortex M3?

    ele
    ele

    Hi 

    Now I'm trying to understand about memories in the Cortex design kit.

    I came across memory address map of cortex M3 when I googling as the below.

    In the image, left one is an AHB memory map, and right one is STM32F103's memory map.

    As you…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Where could I find a good start for studying Memory Types and Attributes as well as Monitors and semaphores ?

    AbdAllah Talaat
    AbdAllah Talaat

    Hi I was studying the memory system ... and I found three related concepts/topics but I couldn't grasphow these concepts are related to each other and to the AMBA Protocol ... these concepts are : - memory Type - memory Attributes - Monitors and semaphores…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the relationship between UART and printf within retarget?

    ele
    ele

    HI.

    I'm trying to understand the relationship between UART and printf within retarget.

    as I understand, retarget supports to implement low level function fputc, if I want to use printf().

    if I am right, I can't still understand the relationship between…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Question about the Pipeline, clock cycle and machine cycle in Cortex-M Series.

    tyskin
    tyskin

    Recently I'm learning the implement of ARM cortex m core in order to optimize my software to be more efficient and be easier to predict its execute time. But now I'm confused about the clock cycle, machine cycle and the pipeline of cortex-m.

    …
    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M3 : what determines the cycle count for a variable cycle count instruction?

    Iain Rist
    Iain Rist

    I have looked at the cycle counts for the Cortex M3 instructions at http://infocenter.arm.com/help/topic/com.arm.doc.100165_0201_00_en/ric1414056333562.html. Some instructions are listed as taking a range of cycles to complete. I want to understand what…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Speculative Branching.

    sammy
    sammy

    Hi, I am new to ARM Cortex M3 Microprocessors. Can somebody please explain me the speculative branching in layman terms.

    Thanks in advance.

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Where can I find the device-specific JTAG instructions for Cortex-M3?

    Muller
    Muller

    I'm trying to communicate with a Cortex-M3 based microcontroller (LPC1769) through JTAG. I already have the hardware required, and have managed to get an example program to work, but to progress further, I need to know the device-specific JTAG instructions…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • why do we need two priviledged modes? cant one do the thing in cortex m3

    sana srikar
    sana srikar

    we have two modes which are privileged in ARM cortex M3 .they are Thread privileged  and handler mode .

    if there is already one privileged mode then why we need the other mode? i mean cant we do work with only one privileged mode?

    is there any difference…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit)

    harshan
    harshan

    Hi Sir,

             Can i change Flash Memory Permission through MPU??

    Thanks and Regards,
    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • coming from AVR 8-bitter,starting ARM CORTEX-M programming

    Luca
    Luca

    Hi everyone, as I wrote in the title, I'm coming from AVR 8-bit MCUs programming and in the last year I learnt a lot about AVR 8-bit architecture,CPU,registers and so on.

    I've done a few projects coding primarily in C and something in Assembly (serial…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Synchronization primitives, do I need CLREX?

    Jan
    Jan

    Hi all,

    I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared variables).

    There are several ressources available…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When will be the Release of "The Definitive Guide to Cortex M7" ??

    harshan
    harshan

    Hi Sir,

    may be the title of this question looks fun, but i am eagerly waiting for your next book "The Definitive Guide to Cortex M7" are you working on this book?? When could i Expect this book

    Thanks and Regards,

    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M3 - Conditions for IT folding

    Remi DUCLOS
    Remi DUCLOS

    Hi folks,

    Some weeks ago, I discover the mechanism of IT instruction folding supported by the cortex-M3.

    As mentionned in 'Cortex-M3 Devices Generic User Guide', "In some situations, the processor can start executing the first instruction in an IT block…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to get Cortex m3 soft core

    Vivek Jayakrishnan
    Vivek Jayakrishnan

    Hi,

    I needed to know where i could get arm cortex m3 soft core. Its for my masters thesis for which i'll be also using Keil uvision 5.

    Thanks in advance

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • View related content from anywhere
  • More
  • Cancel
<>