• 32-bit x 32-bit --->64-bit multiply

    Sean Dunlevy
    Sean Dunlevy

     I managed to produce a 32-bit x 32-bit -->64 bit code fragment that took 18 cycles to complete (it is in-line).


    oldmulshift32:
    lsrs r3,r0,#16 //Factor0 hi [16:31]
    uxth r0,r0 //Factor0 lo [0:15]
    uxth r2,r1 //Factor1 lo [0:15]
    lsrs r1,r1,#16 //Factor1…

    • Answered
    • 1 month ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4 (Thumb2) to M0+ (Thumb) assembly language

    Sean Dunlevy
    Sean Dunlevy

    I have spent a long time trying to find the fastest ARM M0+ macros for C code but I am trying to write an M0+ processor and I have discovered that for an MP3 decoder, the processors ability is it's speed at the polyphase section. Just 9 lines of code…

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M0 (stm32l010) placing interrupt vector in ram for application starting from a proprietary bootloader

    Andrea G. CoopBil
    Andrea G. CoopBil

    Hi all, I follow suggestion red in a forum for overcoming VTOR lack; I did almost all I know, i.e. copyng app.intvec to ram, selecting ram at 0x000,  managing SP register and jumping to app reset vector (all of them with interrupt disabled).

    I'm using…

    • 5 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to speed up DSP processing using Cortex-M0+

    Ponsuke606
    Ponsuke606

    My product is using M0+ core of MCU. And it has FFT and FIR process using CMSIS-DSP. 

    But I faced an issue for performance of these process. It cannot finish doing process within some period of system.

    Is there any ideas or ways to improve performance…

    • Answered
    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • What happens to the Instructions already in pipeline when interrupt occurs ?

    Vijay Kumar Prathipati
    Vijay Kumar Prathipati

    Hello Community,

    Recently I was going through some code and has this doubt.

    My Pseudocode

    ============

    CPSID I - Disable interrupts

    Do critical work

    CPSIE I - Enable interrupts

    Do non critical work.

    After I enabled interrupts and if there is pending interrupt…

    • Answered
    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Programming BRAM with JTAG--Help regarding knowledge source requested.

    Mezan1
    Mezan1

    Hi 

    I am trying to program a BlockRAM inside FPGA using JTAG on spartan 6. I am using core generator provided by Xilinx. Is it possible? Is there any document that I can go through to know how to interface a parallel flash with JTAG? My intention is to…

    • Answered
    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Programming FPGA Block RAM connected to Cortex-M0 using JTAG

    Mezan1
    Mezan1

    Hi,

    I am connecting the BRAM inside FPGA with the Cortex-MO processor. Is it possible to program the BRAM using JTAG? The BRAM will act here as on-chip memory having the memory map of  0x00000000. I do not intend to put the program file in the beginning…

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Off-chip Memory integration with Cortex-M0

    Mezan1
    Mezan1

    Hello 

    I am trying to integrate off-chip memory with the cortex-mo processor. My plan is to attach a  commercial 16 or 8-bit memory with the processor instead of using the on-chip memory. Is it possible that I can attach off-chip memory having the memory…

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Basic Flash Programming and the process in integrating Cortex M0

    Mezan1
    Mezan1

    Hello Guys!

    I am Integrating Cortex-M0 with peripherals and memories. Previously I used Block ROM/RAM in FPGA where I just uploaded COE files to make it run. But now I want to use an external flash to do the Job. I have the following questions which I…

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • IRQ Execution in nRF51

    allen924
    allen924

    Hello

    I am using Seggar Embedded Studio for ARM V3.4 and nRF_SDK 12.3.0.

    I am using nRF51 DK

    I am trying to understand interrupts and interrupt handlers.

    The interrupt request for Watchdog timer (i.e. void WDT_IRQHandler(void)) is not getting executed.…

    • 10 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • How generic are Cortex-M0+ MCUs?

    Oozlum
    Oozlum

    I'm just getting started in the Arm world and I'm trying to get a better understanding of the similarities between various vendor implementations of the Cortex-M0+ at the toolchain level.

    I have previously got a 'blinky' program working on an…

    • 10 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M0--Simple APB peripheral Design (LED)

    Mezan1
    Mezan1

    Hello Guys,

    I connected the peripheral (LED) with cortex-M0 processor and APB BUS using CMSDK in FPGA of the spartan 6 family. I used the AHB-APB bridge to connect it to the processor. I am attaching the peripheral in the code section. I wrote startup…

    • 10 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M0 - Returning from Interrupt

    Mezan1
    Mezan1

    Dear Concern

     I connected the CMSDK timer example with the Cortex - M0 processor. I have written exception handler for a timer in assembly code. After a certain moment interrupt is generated from the timer module in CMSDK. I see that the processor enters…

    • Answered
    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • CortexM0 Debug - DAP baseaddr, M0 ROM Table and system ROM table

    eugch
    eugch

    Hi all,

    Would like to get some clarifications regarding the items above. I'm working on the CMSDK kit for the Cortex M0 and the example system has a Cortex M0, a system ROM table and DAP instantiated.

    The DAP by default has the baseaddr tied to E00F_F003…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • adc read

    gnsh
    gnsh

    AS YOU CAN SEE MY CAPTURE DATA FROM ADC CHANNEL 1 AS PREFIX a20.00000. im perplexed by this result 

    what might be the reason

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • cortex M0 based mcu dac error

    gnsh
    gnsh

    i i am developing cprtex mo based project.

    vendor is nuvoton.

    there  seems to be error  in dac.

    can i reduce the error.

     my dac ouput for input code 000 is 130mv. whose full scale range is 2.5v.

    datasheet has the  folllowing values ,the gain error for typical…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • uart cortex mo

    gnsh
    gnsh

    what is the error

    #include <stdio.h>
    #include "Device\Nuvoton\Nano100Series\Nano100Series.h"
    #include "Device\Nuvoton\Nano100Series\uart.h"
    #include "Device\Nuvoton\Nano100Series\uart.c"
    //#include "Device\Nuvoton\Nano100Series…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Unaligned accesses - CMSDK Example Cortex M0

    eugch
    eugch

    The spec mentions that the M0 will generate a Hardfault when unaligned accesses are detected. I would like to find out where is this implemented in RTL and understand it a little better.

    Does the GCC compiler detects unaligned code accesses during compilation…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • custom board based on cortex M0 toggle pins not responding.

    gnsh
    gnsh

    i am trying to troggle two pins in a custom board built on cortex M0 core( nuvoton nano120 series 120lc2bn)/

    i can get to toggle the given pins.

    pins are pc0 and pb12.

    #include <Device/Nuvoton/NANO1xx/nano1xx.h>

    #include "Device/Nuvoton/NANO1xx…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Fail to connect with CM0DSEvel

    RickyChen
    RickyChen

    I have tryed to make SWD connect to Cortex-M0 DesignStart Eval by STLink2, but it was unsuccessful.

    The SW Device showed information as this picture.

    I chose  AHB_ROM_FPGA_SRAM_MODEL and AHB_RAM_FPGA_SRAM_MODEL be the MYM_TYPE

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M0 Vector Table and Bootloading

    eugch
    eugch

    Hi guys,

    Does the M0 always default to 0x0 when an interrupt triggers? I understand VTOR is not available in M0 for relocation of the tables.

    Can I copy the application vector table just the vector table to beginning of SRAM and remap the SRAM to 0x0…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M Vector Table and Address Remap

    eugch
    eugch

    Hi guys,

    Does the M0 always default to 0x0 when an interrupt triggers? I understand VTOR is not available in M0 for relocation of the tables.

    Can I copy the application vector table just the vector table to beginning of SRAM and remap the SRAM to 0x0…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • STM32F030 CORTEX M0

    Mark
    Mark

    I have initialized the above controller in C++ in Keil 5uV. After the initialization, I want to jump to or enter a timing critical assembly language algorithm under the int main(void) statement. What is the preferred method to accomplish this?

    MJ

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • floating point in cortex m0, always reset.

    willandsmith
    willandsmith

    hi,I write an algorithm running in cortex M0. It has some floating point multiplication.But the program always resets when encounter a floating point multiplication.And the code showed below:

        for (k = 0; k < 4; k++) { tmpx =   dbuffer[0] * a[k + 1…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Concurrent Interrupts

    Michael
    Michael

    Hi All,

    Im new to the Arm Community and Arm processors (newbie), and my question is as follows: Atmel ATSAMD20e  implements ARM cortex M0+ processor based on ARMv6 architecture. It allows upto 32 external interrupts, with the interrupt signals connected…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
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