• ARM CM4 FPU execption

    Anuj
    Anuj

    I am looking for FPU exception generation code. If some one share, or suggest some document for the same.

    Regards

    Anuj

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • cmsis NVIC question.

    Setianian
    Setianian

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Enabling NEON Instructions on Pixhawk

    Nathan Szanto
    Nathan Szanto

    I am trying to get a quadcopter flying using the Pixhawk controller (Cortex M4 running NuttX RTOS) and I am using the Simulink Pixhawk PSP to implement a custom controller. Our controller uses neural networks, so neon instructions are needed (the build…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Race condition between wake up event and WFI on Cortex-M3/M4

    neo
    neo

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to prepare ADC data for Q31_t CMSIS DSP functions?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've another post on the forum (here's the link Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? ), but since I think I made some small steps forward I felt I could be a little more specific. I hope this…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Snake robot with ARM Cortex-M4 processor

    Prashant.Sulakhe
    Prashant.Sulakhe

    I want to design an snake robot with ARM Cortex-M4 processor can u help how to start? please help me.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Loss of information - SMMUL

    Petr
    Petr

    Why the Cortex M4 instruction SMMUL (32 = 32 x 32b) preserves a redundant sign bit and discards one useful bit of information? What could possibly be the justification for such blatant disregard of the ISO/IEC TR 18037 standard Fract format?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Process ADC data, moved by DMA, using CMSIS DSP: what's the right way?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've a firmware running on a NXP LPCLink2 (LPC4370: 204 Mhz Cortex M4 MCU) board which basically does this:

    • Fills the ADC FIFO @40msps.
    • Copies the data into memory using the built-in DMA Controller and 2 linked buffers.
    • Processes one buffer…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Parallelism between CPU and FPU

    Matic
    Matic

    Hi.

    I have a question regarding Cortex-M4 processor with floating point unit. Is it somehow possible to do some computation in parallel in CPU (with integers) and FPU (with floats)?

    Probably not, because both units need their own instructions to perform…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit)

    harshan
    harshan

    Hi Sir,

             Can i change Flash Memory Permission through MPU??

    Thanks and Regards,
    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • VTOR: offset address configuration

    Katsuhiro Atsumi
    Katsuhiro Atsumi

    Core: Cortex-M4F

    Do I need to configure vector table offset address to 0xnnnn_n000?

    In case of 0x3080(Flash region), the program jump to unexpected code.

    I think it is caused by mismatching between vector number and handler address.

    In case of 0x3000(Flash…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Usefulness of MPU in a non-OS system

    Matic
    Matic

    Hi.

    We are developing a product which has to achieve some safety requirements. The system is quite simple, non-OS, running in a Privileged mode only on a Cortex-M4. I would like to implement a Memory Protection Unit somehow. Could you please give any advice…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Memory protection unit - Cortex-M4

    Matic
    Matic

    Hi.

    I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS):

    1. I enabled background region, thus all addressable memory is fully accessible, unless there…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hard Fault in cortex m4

    hemant
    hemant

    Hello All,

    Good Morning!

    I am working on Cortex m4.

    I have read following about hard fault ,

    "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • vfp problem

    Ching Hsiung Yu
    Ching Hsiung Yu

    Hi

    I had a problem.

    I can use vfp in user mode but not work in priviledge level.

    Is there any wrong setting in CP10 , CP11 or any other wrong setting??

    BR

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 exception return sequence

    Gopal Amlekar
    Gopal Amlekar

    Hi,

    I think I am just getting confused with this even if (or because of) I read the book and manuals again and again.

    At exception entry, the processor saves R0-R3, R12, LR, PC and PSR on the stack. Saving PC means that the address of the instruction to…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How long bitfields on which ARM?

    Øyvind Teig
    Øyvind Teig

    I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

    Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Help me jump into ARM world !(I know nothing but AVR)

    kamran
    kamran

    Hi,  Sorry if this is a long thread but i'm really confused.

    I program for AVR MCUs and also know about Arduino, I can program for different ATMEL MCUs with looking at datasheets, And i also programmed a few basic stuff on Cortex-M3 LPC1768, without…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • serial wire debug

    harshan
    harshan

    sir,

         I am working with SWD(serial wire debug protocol) on cortex m4 architecture, one thing  i don't understand that i am unable to write value into registers r13 and r14 the remaining registers all are updating but for r13 and r14 i am unable to…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • updating CPSR in USER UNPRIVILEGED mode

    anoop
    anoop

    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Indication to begin a program

    amrani joutei
    amrani joutei

    I need some indications to begin writing a program.

    Write a compare routine to compare 64-bits values , using only two instructions.

    Thanks for your indications !

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Break Points and Watch Points

    harshan
    harshan

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Get current active interrupt priority

    Jonathan Weber
    Jonathan Weber

    Hi everybody,

    We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.

    In our implementation we need to determine…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to acknowledge/clear active interrupt in Cortex-M4

    Deepak Jharodia
    Deepak Jharodia

    Hi all,

    I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M7 "zero overhead loop"

    Ari Mendes
    Ari Mendes

    Hi.

    In the page 22 of the document below informs that the cortex-m7 has "zero overhead loops" capability. I would like to know how it is done? Is there a special instruction for it?

    http://community.arm.com/servlet/JiveServlet/downloadBody/9595…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
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